An ADPLL circuit using a DDPS for genlock applications

Abstract

This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12MHz and 200MHz, with a frequency between 24Hz and 100MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator. The measured jitter at the output is between 184 and 274ps (depending on control parameters). The circuit is implemented in 0.18µm CMOS technology and dissipates 50mW when running at 150MHz.

A 20kHz frequency resolution DCO

“…The CP and analog LPF of the analog PLL are no longer required. The ADPLL divider can be the same as the divider in an analog PLL [7]- [12]. The Digital Loop Filter is shown in Figure 2.1 1 [3] For each "up" pulse generated by the phase detector, the counter is increased by 1 .…”

“…12 shows the output signal follows the input "b" when the "select" is high; when the "select" is low, the output follows input "a". Simulated MUX Gate61 The XOR gate (used to construct the switching block) is drawn inFigure 4.13 and the simulated waveform is shown inFigure 4.14.…”