An Advanced 2.5nm Oxidized Nitride Gate Dielectric For Highly Reliable 0.25/spl mu/m MOSFETs

Yamamoto,; Ogura,; Saito,; Uwasawa,; Tatsumi,; Mogami,

doi:10.1109/vlsit.1997.623687

Cited by 9 publications

(4 citation statements)

References 3 publications

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“…Compared with N2O_1, the further improvement in leakage current reduction is not obvious for N2O_2. This phenomenon can be mainly ascribed to the fact that, for N2O_1, the subsequent wet oxidation process oxidizes the upper part of the CVD-based nitride film and partially due to the reduced electron trap density of the CVDbased nitride film in the wet oxidizing ambient [12], [13], and thereby reducing the difference between N2O_1 and N2O_2. Since wet oxidation only improves the CVD-based nitride, the N 2 O treatment of the thermally grown nitride is necessary to further enhance its quality, and is evidenced by the comparison of the leakage current presented in Fig.…”

Section: Resultsmentioning

confidence: 99%

Augmented Cell Performance of NO-Based Storage Dielectric by N<formula formulatype="inline"><tex>$_2$ </tex></formula>O-Treated Nitride Film for Trench DRAM

Chang

Wang

et al. 2008

IEEE Electron Device Lett.

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Owing to the delayed introduction of high-k storage dielectric for trench DRAM, a new technology to extend the existing NO storage dielectric becomes a prerequisite. For trench DRAM, the nitride film of NO-based storage dielectric has been proved to possess higher quality by proper N 2 O treatment, which enables further reduction in nitride thickness and extension of scaling limit for the existing storage dielectric. A 164% leakage current improvement without sacrificing the cell capacitance can be achieved through this process, while keeping the outstanding reliability performance of less than 438 ppm failure rate after a ten-year operation. Most importantly, this new process can be fully integrated into incumbent furnace process, which means that no additional tool investment is required, and it is crucial for trench DRAM manufacturers to maintain their competitive advantage before the high-k material prevails at 65 nm technology node.

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Section: Resultsmentioning

confidence: 99%

Augmented Cell Performance of NO-Based Storage Dielectric by N<formula formulatype="inline"><tex>$_2$ </tex></formula>O-Treated Nitride Film for Trench DRAM

Chang

Wang

et al. 2008

IEEE Electron Device Lett.

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“…Due to such aggressive scaling, thickness of gate dielectric is reduced below 4 nm down to 2 nm [1], [3]. These gate dielectrics are subjected to very high electric field during circuit operation.…”

Section: Introductionmentioning

confidence: 99%

“…An attempt is made to search for such reliable gate dielectric keeping low thermal budget. Nitrogen incorporation at Si-SiO2 interface is known to improve interface stability [3], [6]- [12]. Nitrogen incorporation can be achieved by various methods, such as NH 3 nitridation of control oxide [7], [11], [12], growth (or annealing) of oxide in N2O or NO ambient [7]- [9], etc.…”

Section: Introductionmentioning

confidence: 99%

Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

Borse

Vaidya

Chandorkar

2002

IEEE Trans. Electron Devices

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Abstract-This paper reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22 C to 90 C) has been investigated. The effect of nitrogen annealing (20 min) at 400 C on high temperature stress-induced interface traps was also studied.Index Terms-Oxynitrides, SILC, temperature dependence of interface trap generation, ultra-thin oxides.

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“…Furthermore, SiO 2 is not a good diffusion barrier for gate electrode dopants, such as boron. Even with nitrogen incorporation, 1,2 it is difficult to utilize ultrathin nitrided oxides for sub-quarter-micrometer technologies due to high tunneling current and rough Si-SiO 2 interface. Therefore, when the SiO 2 thickness is reduced to below 2 nm, alternate high-permittivity ͑k͒ dielectrics such as Ta 2 O 5 , HfO 2 , and ZrO 2 must be considered.…”

mentioning

confidence: 99%

Atomic Layer Deposition of High Dielectric Constant Nanolaminates

Zhang¹,

Solanki²

2001

J. Electrochem. Soc.

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Thin stacks comprised of alternating layers of Ta 2 O 5 /HfO 2 , Ta 2 O 5 /ZrO 2 , and ZrO 2 /HfO 2 were investigated as high-permittivity insulators for possible gate dielectric applications. These thin layers were deposited on silicon substrates using atomic layer deposition. Nanolaminates with silicon oxide equivalent thickness of about 2 nm had dielectric constants of around ten and leakage current densities at 1 MV/cm of around 10 Ϫ8 A/cm 2 . Of the three kinds of nanolaminates investigated, ZrO 2 /HfO 2 structures showed the highest breakdown field and the lowest leakage current.The continuous downscaling of metal-oxide-semiconductor field effect transistors ͑MOSFETs͒ requires a corresponding reduction of the gate dielectric thickness. As a result of this reduction, direct tunneling current through the silicon dioxide gate dielectric is becoming a very serious issue. The current generation of MOSFETs with channel length of 0.18 m requires a proportional decrease in the oxide equivalent thickness of the gate insulator to less than 3 nm. A major limiting factor in transistor scaling beyond the current 0.18 m design rules has been the difficulty of growing highquality, ultrathin oxides as the tunneling limit of 2.5 nm for SiO 2 is approached and gate leakage currents exceed 1 A/cm 2 . Furthermore, SiO 2 is not a good diffusion barrier for gate electrode dopants, such as boron. Even with nitrogen incorporation, 1,2 it is difficult to utilize ultrathin nitrided oxides for sub-quarter-micrometer technologies due to high tunneling current and rough Si-SiO 2 interface. Therefore, when the SiO 2 thickness is reduced to below 2 nm, alternate high-permittivity ͑k͒ dielectrics such as Ta 2 O 5 , HfO 2 , and ZrO 2 must be considered. Ta 2 O 5 has been investigated as the capacitor dielectric in gigabit dynamic random access memory chips ͑DRAMs͒. 3-5 Recently MOSFET devices have also been fabricated using high-k thin films including Ta 2 O 5 , HfO 2 , and ZrO 2 . 6-9 One major obstacle in using high-k materials is that a solid material with higher permittivity tends to have a narrower bandgap. This is deduced from a reduced cohesive force according to the quantummechanical consideration, 10 thereby suffering from a larger leakage current. We have previously reported a remarkable improvement of binary high-permittivity oxides by preparing nanolaminates which were composed of alternate layers of Ta 2 O 5 /HfO 2 , Ta 2 O 5 /ZrO 2 , and ZrO 2 /HfO 2 . 11 In this paper we present our recent results on properties of much thinner nanolaminates as dielectrics in metaloxide-semiconductor capacitor ͑MOSCAP͒ structures.These films were deposited using the unique self-limiting growth process of atomic layer deposition ͑ALD͒ that allows film growth one atomic layer at a time from multiple source materials at relatively low temperatures. In this process one reactant at a time is injected into the growth area, and following surface reaction, excess species and by-products are purged with an inert gas. As a result, films are grown by se...

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An Advanced 2.5nm Oxidized Nitride Gate Dielectric For Highly Reliable 0.25/spl mu/m MOSFETs

Cited by 9 publications

References 3 publications

Augmented Cell Performance of NO-Based Storage Dielectric by N<formula formulatype="inline"><tex>$_2$ </tex></formula>O-Treated Nitride Film for Trench DRAM

Augmented Cell Performance of NO-Based Storage Dielectric by N<formula formulatype="inline"><tex>$_2$ </tex></formula>O-Treated Nitride Film for Trench DRAM

Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

Atomic Layer Deposition of High Dielectric Constant Nanolaminates

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