Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

Abstract

Abstract-This paper reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22 C to 90 C) has been investigated. The effect of nitrogen annealing (20 min) at 400 C on high temperature stress-induced interface traps was also studied.Index Terms-Oxynitrides, SILC, temperature dependence of interface trap generation, ultra-thin oxides.

Optical Subthreshold Current Method for Extracting the Interface States in MOS Systems

“…I NTERFACE state in MOS systems is one of the most critical parameters in MOS devices [1]- [3]. It has been typically evaluated from MOS capacitors using the capacitance-voltage measurement, conductance technique, deep level transient spectroscopy, and others.…”

Charge Pumping Technique to Measure Polarization Switching Charges of FeFETs

“…8(a). As the interface traps of a well-controlled MOSFET does not exceed 5 × 10 12 cm −2 •eV −1 , the measured charge can be estimated using the components other than the additionally included interface traps [22,23]. The calculated number of gate charges (Ngate), S/D charges (NSD), and well charges (Nwell) from the current components measured under the conventional triangular pulse are illustrated in Fig.…”

Analysis on Temperature Dependence of Hot Carrier Degradation by Mechanism Separation

“…Generally, interface traps are formed with specific distributions within the bandgap [14]. Therefore, as V GS increases, S.S. changes due to the increase of interface traps involved in V TH shift.…”