An aggressive power optimization of the ARM9-based core using RAZOR

Abstract

With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental noise. On the other hand, as long as all errors can be detected and recovered, a considerable amount of energy can be saved.In this paper, a processor based on the ARM architecture was first implemented and verified, and then the RAZOR technique was integrated to add resiliency. The core with and without RAZOR are then simulated using an FFT program at different supply voltages and clock frequencies.The optimized core achieved a maximum energy reduction of 22% at constant clock frequency, while a 23% performance increase is observed at constant energy consumption.

Delay variation compensation through error correction using razor

“…These testbenches typically involve thousands of clock cycles to finish which is ideal for quantifying error rates. The simulation results shown in Section II were generated using a simple FFT program [1], [2] providing a good instruction mix of dataprocessing instructions which allows the simulation of data dependent errors. Given a more thorough testbench would greatly improve the characterization of the error correction technique.…”

“…The Razor technique is integrated to the ARM9 core by replacing critical path, execute stage, pipeline registers with Razor flipflops [2]. By targetting only the critical path registers, specifically the ones capturing the ALU output, the number of Razor flipflops in the processor are minimized, leading to lower power overhead.…”

“…Moreover, the ARM9 core was also modified to utilize only single-edge triggered flipflops to minimize additional delay considerations introduced by its dual-edge counterparts [4]. Figure 2, generated from an earlier work [2], shows the comparison of the area of operations available to the two cores: the base ARM9 and the ARM9 with Razor. The base ARM9 core can only operate in a very limited area when being compared to the ARM9 core with error correcting mechanism.…”

“…The power overhead of the Razor technique is most evident if errors do not occur. However, this power overhead is rather insignificant, around 3% and 9% from two implementations utilizing Razor [1], [2]. The benefit of Razor can be seen when wide-range PVT variations were applied, which robust sensor nodes are expected to be resilient against.…”

“…Comparison of the region of operations of the two processors[2]. The colors represent the energy with values indicated in the right axis.…”