With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental noise. On the other hand, as long as all errors can be detected and recovered, a considerable amount of energy can be saved.In this paper, a processor based on the ARM architecture was first implemented and verified, and then the RAZOR technique was integrated to add resiliency. The core with and without RAZOR are then simulated using an FFT program at different supply voltages and clock frequencies.The optimized core achieved a maximum energy reduction of 22% at constant clock frequency, while a 23% performance increase is observed at constant energy consumption.

The delay dependency of digital circuits on process, voltage and temperature variations are usually compensated by using safety margins that set the limit of operating supply voltage or clock frequency. Razor enables the processor to operate beyond this safety margin through the utilization of error detection and recovery circuits. In this paper, a single chip dual ARM9 core solution, with and without Razor, is implemented in 65nm CMOS to accurately characterize the added resiliency introduced by Razor. Functionality testing on the same operating environment allows for a fair characterization by isolating delay dependencies caused by PVT variations.