An Algebraic Model of Fault-Masking Logic Circuits

Schwab,; Yau,

doi:10.1109/tc.1983.1676330

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1986

2008

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Cited by 6 publications

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“…At this level, however, it is possible to take advantage of the intrinsic error masking capabilities of logic gates in order to avoid the explicit introduction of voting elements. With typical gate-level approaches to fault-tolerance (such a s quadded-logic [3] and interwoven-redundancy [4]) logic gates (or subcircuits) are replicated and interconnected in a way that prevents the propagation of logic errors caused by internal faults [3,4,5,6,7]. System-and gate-level techniques preserve the topology of the original system.…”

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confidence: 99%

Synthesis of multilevel fault-tolerant combinational circuits

Bogliolo¹,

Damiani²

Proceedings the European Design and Test Conference. ED&TC 1995

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In this paper we present a new approach to the design of multilevel fault-tolerant circuits. The approach is based on introducing a minimal amount of fault-masking redundancy during a multilevel logic optimization process. This is done by taking into account the degrees of freedom associated with internal don't care c onditions. Experimental results obtained on several benchmark circuits compare very favourably with fault-tolerant implementations based o n t r aditional gate-level strategies.

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confidence: 99%