Synthesis of multilevel fault-tolerant combinational circuits

Abstract

In this paper we present a new approach to the design of multilevel fault-tolerant circuits. The approach is based on introducing a minimal amount of fault-masking redundancy during a multilevel logic optimization process. This is done by taking into account the degrees of freedom associated with internal don't care c onditions. Experimental results obtained on several benchmark circuits compare very favourably with fault-tolerant implementations based o n t r aditional gate-level strategies.