An algorithm-driven processor design for video compression

Molloy, S.; Schoner, B.; Madisetti, A.; Jain, Rajeev; Matic, Roy M.

doi:10.1109/icip.1994.413733

Proceedings of 1st International Conference on Image Processing

DOI: 10.1109/icip.1994.413733

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An algorithm-driven processor design for video compression

S. Molloy¹,

B. Schoner²,

A. Madisetti³

et al.

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Cited by 2 publications

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“…Our approach is similar to the CORDIC-based FIR, IIR, and DCT architectures in the literature [8]- [10], but the functionality is much more general-purpose. It can be classified as the algorithm-driven solution [11] since the programmability and ASIC-like processing speed of our design are achieved by fully exploiting the inherent properties of the given DSP algorithms. Besides, the proposed architecture is very suitable for VLSI implementation due to its modularity and regularity.…”

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confidence: 99%

System architecture of an adaptive reconfigurable DSP computing engine

Liu

Raghupathy

1998

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-Modern digital signal processing (DSP) applications call for computationally intensive data processing at very high data rates. In order to meet the high-performance/lowcost constraints, the state-of-the-art video processor should be a programmable design which performs various tasks in video applications without sacrificing the computational power and the manufacturing cost in exchange for such flexibility. Currently, general-purpose programmable DSP processor and applicationspecific integrated circuit (ASIC) design are the two major approaches for data processing in practical implementations. In order to meet the high-speed/low-cost constraint, it is desirable to have a programmable design that has the flexibility of the general-purpose DSP processor while the computational power is similar to ASIC designs. In this paper, we present the system architecture of an adaptive reconfigurable DSP computing engine for numerically intensive front-end audio/video communications. The proposed system is a massively parallel architecture that is capable of performing most low-level computationally intensive data processing including finite impulse response/infinite impulse response (FIR/IIR) filtering, subband filtering, discrete orthogonal transforms (DT), adaptive filtering, and motion estimation for the host processor in DSP applications. Since the properties of each programmed function such as parallelism and pipelinability have been fully exploited in this design, the computational speed of this computing engine can be as fast as ASIC designs that are optimized for individual specific applications. We also show that the system can be easily configured to perform multirate FIR/IIR/DT operations at negligible hardware overhead. Since the processing elements are operated at half of the input data rate, we are able to double the processing speed on-the-fly based on the same system architecture without using high-speed/fullcustom circuits. The programmable/high-speed features of the proposed design make it very suitable for cost-effective video-rate DSP applications.Index Terms-Coordinate rotation digital computer (COR-DIC), discrete cosine transforms, FIR digital filters, IIR digital filters, multirate processing, quadrature mirror filter, reconfigurable architectures.

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System architecture of an adaptive reconfigurable DSP computing engine

Liu

Raghupathy

1998

IEEE Trans. Circuits Syst. Video Technol.

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Algorithm-based low-power and high-performance multimedia signal processing

Liu

Raghupathy

et al. 1998

Proc. IEEE

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An algorithm-driven processor design for video compression

Cited by 2 publications

References 8 publications

System architecture of an adaptive reconfigurable DSP computing engine

System architecture of an adaptive reconfigurable DSP computing engine

Algorithm-based low-power and high-performance multimedia signal processing

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