We present a low-power design methodology based on the multirate approach for DSP systems. Since the data rate in the resulting multirate implementation is M-times slower (where M is a positive integer) than the original data rate while maintaining the same throughput rate, we can apply this feature to either the low-power implementation, or the speed-up of the DSP systems. This design methodology provides VLSI designers a systematic way to design low-power DSP systems at the algorithmic/architectnral level. The proposed low-power multirate design scheme is verified by the implementation of two FIR VLSI chips with different architectures: One is the normal pipelined design and the other is the multirate design with downsampling rate equal to two. The experimental results show that the multirate FIR chip consumes only 21% power of the normal FIR chip given the same data throughput rate.

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In the current study, a network-based resistor model has been developed for thermal analysis of a complex optoelectronic package called SFP (Small Form-factor Pluggable Device). This is done using the DELPHI (DEvelopment of Libraries of PHysical models for an Integrated design) Methodology. The SFP is an optical transceiver widely used in telecommunication equipments such as switches and routers. The package has a detailed construction, and typically has four heat generating sources. The detailed model for the SFP is constructed and validated using a natural convection experiment. The validated detailed model is used for generating the Boundary-Condition-Independent (BCI) Compact Thermal Model (CTM). Codes for solving the network topology and interfacing with the optimization subroutine were written using Matlab 7. The resulting CTM is extensively validated with multiple boundary condition sets. The CTM for the SFP shows maximum relative of errors less than 10% for the junction temperature on all of its active components and less than 20% for the heat flows through its sides for extreme set of boundary conditions.