An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering

Watanabe, Toshio; Mizuno, Tomohisa; Makino, Y.

doi:10.1109/jssc.2002.806263

Cited by 127 publications

(89 citation statements)

References 17 publications

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“…One of the major challenges in developing digital voltage sensors is to design highly sensitive CDEs. Watanabe et al [6] proposed an all-digital ADC in which the CDE architecture is based on the CMOS square-law behavior. Furthermore, the transistor drain current depends considerably on the supply voltage, and thus, the charging and discharging currents on the external capacitor inserted at the inverter output can be managed by controlling the supply voltage.…”

Section: Related Workmentioning

confidence: 99%

“…Fig. 1(c) shows the characteristic of the CDEs prepared in previous works [6,7] using a 32-nm CMOS predictive technology model (PTM) [13] supplied with 0.9-V VDD with a 10 fF capacitor. This figure shows that the delay can be well-controlled using either a power supply-control method or a current-starved inverter technique when input voltage (V IN ) ranges from 0.5 to 0.8 V. However, the delay controllability will be reduced significantly if V IN fluctuates within the 0.1 V range around the supply voltage (i.e., 0.8 to 1.0 V).…”

Section: Related Workmentioning

confidence: 99%

“…As a result, these techniques are not suitable for voltage sensor applications in which V IN usually fluctuates by ±10% around the VDD. Watanabe et al noted that the fluctuating voltage range used in the ADC is around 1.8 to 2.0 V [6], whereas VDD is 5 V; the input range is also much smaller than VDD = 2V in Taillefer and Roberts [7].…”

Section: Related Workmentioning

confidence: 99%

“…Numerous designs have been proposed for fully digital voltage sensors and analog-to-digital converters (ADCs) because they are widely preferred to achieve noise immunity [4][5][6][7]. However, to the best of our knowledge, a FinFET-based digital voltage sensor has yet to be developed.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

Nguyen¹,

Kim

2016

IEIE Transactions on Smart Processing and Computing

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Abstract:In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

Nguyen¹,

Kim

2016

IEIE Transactions on Smart Processing and Computing

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“…However, this approach has a drawback of a nonlinear relationship between control voltage and propagation delay. Another approach to implement a delay cell is to use power supply controlled inverter [12] as shown in Fig. 2-b.…”

Section: The Controllable Delay Element (Cde)mentioning

confidence: 99%

A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications

Ryu

Kim

2013

IEICE Electron. Express

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This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high linearity and high resolution. The proposed CDE uses power supply node to measure the voltage value. However, the delay increases exponentially at low voltage level. In this paper we add a PMOS header in parallel with the conventional CDE to compensate the delay degradation at lower voltage. We develop a 16-levels fully digital voltage sensor with a voltage range of 0.8 ∼ 1.1 V and 20 mV resolution by using of the proposed delay elements. The proposed circuit is designed and simulated in a 45 nm CMOS process. The simulation results show the feasibility of the high resolution and high linearity at low voltage by using of the proposed delay elements.

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Oversampled ADC Using VCO‐Based Quantizers

Hueber

Staszewski

2010

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications

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An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering

Cited by 127 publications

References 17 publications

Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications

Oversampled ADC Using VCO‐Based Quantizers

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