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A novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs). This fabrication technique is based on the high-temperature oxidation of the SGOI layers with a lower Ge fraction. It is found that Ge atoms are rejected from the oxide and condensed in the SGOI layers. The conservation of the total amount of Ge atoms in the SGOI layer is confirmed by structural and compositional analyses of dry-oxidized SGOI layers at 1050°C of different initial thicknesses and oxidation times. Using this technique, a 16-nm-thick SGOI layer with the Ge fraction as high as 0.57 is successfully obtained. The Ge profiles across the SGOI layers are quite uniform and the layers are almost completely relaxed. Significant dislocation generation in the SGOI layer is not observed after the oxidation. This is a promising technique for application to sub-100 nm fully-depleted silicon-on-insulator (SOI) MOSFETs with strained-Si or SiGe channels.

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We have experimentally studied the surface orientation/strain effects on quantum mechanical confinement (QMC) in two-dimensional (2D) Si layers with thicknesses less than the Si lattice constant for future metal–oxide–semiconductor (MOS) devices. By UV–Raman spectroscopy, we have demonstrated that the quantum phonon confinement effects (PCEs) rapidly increase with decreasing 2D Si thickness T S, but is almost independent of surface orientation and strain. Thus, electron saturation velocity of the 2D Si is degraded by the reduced phonon energy owing to the PCEs. On the other hand, photoluminescence (PL) emitted from the only (100)-surface 2D Si layers, depends on the excitation photon energy hν (2.33≤hν≤3.81 eV), and PL intensity increases with decreasing T S. The PL data can be explained by simple PL models considering the electron/hole pair recombination mechanism. Consequently, it is necessary to reconstruct the device design for future Si devices, considering the T S dependence of the 2D Si properties.