An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs

Sadi, Mehdi; Conroy, Zoe; Eklow, B.; Kamm, Matthias; Bidokhti, Nematollah; Tehranipoor, Mohammad

doi:10.1109/ats.2014.64

Cited by 5 publications

(1 citation statement)

References 19 publications

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“…Since the speed of the buffers, used in the delay line, is sensitive to power supply noise and voltage droop, we analyzed the power supply variation sensitivity of the sensor IP and tabulated the results in Table 1. The effect of voltage droop -slowing down of the sensor as shown for the 90% VDD case in Column 3 -can be easily decoupled from slack data with the aid of power supply noise sensors such as in [19].…”

Section: Resultsmentioning

confidence: 99%

Speed Binning Using Machine Learning And On-chip Slack Sensors

Sadi

Tehranipoor

Wang

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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Speed binning of integrated circuits using Fmax test of a SoC requires application of complex functional and structural test patterns. Today's test-pattern-based speed binning techniques incur high test cost in terms of long test time and requires significant effort to generate effective patterns. In this paper we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/near-critical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmax values from a set of randomly tested die during wafer sort. The proposed flow has been demonstrated in a SoC circuit at 28/32nm technology. The worst-case miss-binning of the predictor is within 6% of the nominal Fmax.

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Section: Resultsmentioning

confidence: 99%