An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication

Kim, Taeyeon; Choi, Sung-Uk; Han, Sangwoo; Kim, Jongsun

doi:10.1109/isocc50952.2020.9332935

Cited by 1 publication

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, [10] has a problem in that the N/M-ratio programmability is limited because it uses simple flip-flop-based counter dividers with large area and power consumption. This paper introduces a new wide-range N/M-ratio MDLL clock generator using a new Pseudo-NMOS comparator-based programmable divide-by-N divider [16]. The proposed divide-by-N divider has the advantages of small area, low power, and high-speed operation, while providing wide programmable division ratios.…”

Section: Selectmentioning

confidence: 99%

“…The CDL consists of sixteen digital delay elements (DEs) connected in series. When the MDLL is enabled, the PD generates the Comp signal by comparing the N + 1th rising edge of CLKOUT and the M + 1th rising This paper introduces a new wide-range N/M-ratio MDLL clock generator using a new Pseudo-NMOS comparator-based programmable divide-by-N divider [16]. The proposed divide-by-N divider has the advantages of small area, low power, and high-speed operation, while providing wide programmable division ratios.…”

Section: Proposed Digital Mdll Architecturementioning

confidence: 99%

“…Also, the trade-off between the PLL's loop bandwidth and stability makes it challenging to generate wide-range output clock frequencies in a single integer-N PLL. Electronics 2022, 11, 261. https://doi.org/10.3390/electronics11020261 https://www.mdpi.com/journal/electronics Among various on-chip clock generators, multiplying delay-locked loops (MDLLs) can be considered as a way to implement the N/M-ratio frequency multiplication while improving the jitter performance with reduced loop bandwidth issues [4][5][6][7][8][9][10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

“…In addition, whenever the reference CLK IN is injected, the jitter accumulated in the VCO is removed, and the jitter and phase noise characteristics of the MDLL are improved. Among various on-chip clock generators, multiplying delay-locked loops (MDLLs) can be considered as a way to implement the N/M-ratio frequency multiplication while improving the jitter performance with reduced loop bandwidth issues [4][5][6][7][8][9][10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

Kim

2022

Electronics

Self Cite

View full text Add to dashboard Cite

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

show abstract

Section: Selectmentioning

confidence: 99%

Section: Proposed Digital Mdll Architecturementioning

confidence: 99%