An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

Ishibashi, K.; Yamanaka, Toshiaki; Shimohigashi, K.

doi:10.1109/4.50284

Cited by 25 publications

(3 citation statements)

References 6 publications

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“…The SRAM cell stability is improved by Ishibashi et al in [17] using a Polysilicon PMOS load (PPL) cell. Lohstroh exploited the stable phenomenon of the Flip-Flop equation based on the worst-case static noise margin criteria [l8].…”

Section: Readsmentioning

confidence: 99%

A new design methodology for multiport SRAM cell

Lai

Chuang

Chen

1994

IEEE Trans. Circuits Syst. I

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In this paper, we propose a new design methodology for multiport SRAM cell. A traditional static 6T CMOS cell is adapted to the multiport SRAM cell by adding several wordline transistors, thereby allowing asynchronous reads and writes during an operands access stage using the read feature of the 5T cell and the write feature of the 6T cell. The stability of the SRAM cell is affected by the factors of p-transistor, n-transistor and passtransistor, not by the absolute dimensions of the three transistors. The optimal read access curve can be used to obtain the fastest access time in the secure range for the general multiport SRAM cell.

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Section: Readsmentioning

confidence: 99%

A new design methodology for multiport SRAM cell

Lai

Chuang

Chen

1994

IEEE Trans. Circuits Syst. I

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“…A TFT load cell is suitable for high-density low-power static RAM'S [2], however, the operating voltage of the cell is as high as 2 V, as shown in our previous report [3]. We have developed a new 1-V SRAM using a 10.2-pm2 TFT load cell.…”

Section: Introductionmentioning

confidence: 95%

A 1-V TFT-load SRAM using a two-step word-voltage method

Ishibashi

Takasugi

Yamanaka

et al. 1992

IEEE J. Solid-State Circuits

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A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a twostep word-voltage (TSW) method, a submicroampere boostedlevel generator using a multivibrator, and a sense amplifier using low-threshold MOSFET's. An access time of 250 ns and a standby current of 0.23 pA were achieved for a 4-kb test chip using a 10.2-pm2 TFT-load cell. This technology is applicable for high-density and single-battery operational SRAM's.'A 23-11s 4-Mb CMOS SRAM with 0.2-pA standby

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“…We implement our safe storage cells using a six-transistor cell to maximize the static noise margin (SNM) since SNM is a good measure of the amount of spurious signal needed at the memory cell inputs to corrupt its state. The SNM of different memory cell configurations has been studied [2], showing that the 6T configuration is the best choice to maximize SNM if higher EMI tolerance system is needed [3,4].…”

Section: Introductionmentioning

confidence: 99%

TERPS: the embedded reliable processing system

Wang¹,

Rodriguez²,

Dirik³

et al.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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-TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TERPS tolerates EMI by periodically checkpointing processor state into a special safe-storage device. The detection of EMI invokes rollback, which recovers processor state from a previously check-pointed state and resumes normal execution. Rollback results in loss of performance dictated by the EMI duration; TERPS ensures forward progress of the system provided EMI events are separated by some minimum time interval (e.g., at least 5.12µ µ µ µs for our prototype processor running at 100MHz). The performance overhead of our mechanism is reasonable: 5-6% overhead when checkpointing every 128 processor cycles.

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An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

Cited by 25 publications

References 6 publications

A new design methodology for multiport SRAM cell

A new design methodology for multiport SRAM cell

A 1-V TFT-load SRAM using a two-step word-voltage method

TERPS: the embedded reliable processing system

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