An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

Abstract

This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits are modeled as a composition of controlled sources. Unlike other VHDL-based analog simulation methods, these MixED sources compute not only a real number representing an output voltage but also an output impedance. This allows the outputs of several MiXED sources to be connected in order to drive the same node signal . The voltage of this record-type signal is automatically computed at its element by resolution functions in compliance with Kirchhoff's current law. The data structure of the node signal , its self-defined resolution functions, and an associated driver component are presented and discussed to meet different simulation requirements, such as speed, versatility, current accuracy, and adaptive time stepping. Several examples demonstrate how to behaviorally model mixed-signal components with this method with an emphasis on the simulation of a heterodyne receiver. Simulation speeds are compared to VHDL-AMS tools.Index Terms-Analog, mixed signal, modeling, RF, RF integrated circuit (RFIC), simulation, system on a chip (SoC), verification, very-high-speed integrated-circuit hardware description language (VHDL).

Modeling static analog behavior for determining mixed-signal test coverage using digital tools

“…As before in Listing 5, the sar logic contains 244 faults which are classified as either not-detected or possibly detected, 221 and 23, respectively. sn [2] 128 I bn [7] 256 I sn [1] As previously reported, the coverage of the sar logic is the same for the all-codes or major-carry tests. However, the faults in the DAC are covered by the "exhaustive" analog test of converting ADC input levels to all output codes.…”

“…Modeling analog behavior and circuits for digital simulation tools has received some significant attention in the research community [7]. In [8], the author has presented a method for modeling a SAR ADC for mixed-signal design simulations employing an event-driven Verilog simulator.…”

On Event Driven Modeling of Continuous Time Systems

“…Event driven behavioral modeling [2], prominently recognized as Real Number Models (RNMs), come as an answer to such verification needs. Available in various flavors in verification oriented HDLs such as e [3], SystemVerilog [4]- [6], VHDL [7] and so on, their essential strength lies in the fact that their evaluation is triggered based on discrete "events", so to say, instead of the traditional continuous time evaluations done by SPICE simulators. Referring back to the earlier example of the capacitive buck, the evaluation for the analog model would be triggered only on changes in trim setting, external loading or violation of output voltage limits.…”

Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

“…Substantial oversampling is thus needed, reducing the speed of the model. A second approach to model and simulate linear and non-linear analog circuits is to use an event-based analog solver technique [19]- [21]. However, these models are circuit specific, require special software, or use look-up tables.…”