An Analysis of Persistent Memory Use with WHISPER

Abstract

Emerging non-volatile memory (NVM) technologies promise durability with read and write latencies comparable to volatile memory (DRAM). We define Persistent Memory (PM) as NVM accessed with byte addressability at low latency via normal memory instructions. Persistent-memory applications ensure the consistency of persistent data by inserting ordering points between writes to PM allowing the construction of higher-level transaction mechanisms. An epoch is a set of writes to PM between ordering points. To put systems research in PM on a firmer footing, we developed and analyzed a PM benchmark suite called WHISPER (Wisconsin-HP Labs Suite for Persistence) that comprises ten PM applications we gathered to cover all current interfaces to PM. A quantitative analysis reveals several insights: (a) only 4% of writes in PM-aware applications are to PM and the rest are to volatile memory, (b) software transactions are often implemented with 5 to 50 ordering points (c) 75% of epochs update exactly one 64B cache line, (d) 80% of epochs from the same thread depend on previous epochs from the same thread, while few epochs depend on epochs from other threads. Based on our analysis, we propose the Hands-off Persistence System (HOPS) to track updates to PM in hardware. Current hardware design requires applications to force data to PM as each epoch ends. HOPS provides high-level ISA primitives for applications to express durability and ordering constraints separately and enforces them automatically, while achieving 24.3% better performance over current approaches to persistence.

Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems

“…However, epoch barriers incur non-trivial overhead to the cache hierarchy. Furthermore, system performance can be sub-optimal with small epoch sizes, which is observed in many persistent memory workloads [11]. Our design uses lightweight hardware changes on existing processor designs without expensive non-volatile on-chip transaction buffering components.…”

“…We evaluate both singlethreaded and multithreaded versions of each benchmark. In addition, we evaluate the set of real workload benchmarks from the WHISPER persistent memory benchmark suite [11]. The benchmark suite incorporates various workloads, such as key-value stores, in-memory databases, and persistent data caching, which are likely to benefit from future persistent memory techniques.…”

“…Reaping its full potential is challenging. Previous persistent memory designs introduce large performance and energy overheads compared to native memory systems, without enforcing consistency [11], [12], [13]. A key reason is the write-order control used to enforce data persistence.…”

Ribbon

“…Software Cache [36] implements a resizable cache to combine writebacks and reduce CLF. Hardware modifications in the cache hierarchy and new instructions [39,49] are also proposed to reduce the latency of CLF. Also, some cache designs use (relaxed) non-volatile memories [44,50,51], which naturally eliminates CLF.…”

Distributed Logless Atomic Durability with Persistent Memory

“…Software logging uses flush instructions such as clwb to write the logs to PM before any in-place data updates become persistent [5,6,13,15,17,22,25,30,42,43]. Kamino-TX [27] instead maintains a replica of the dataset to serve as an undo log, thus removing logging from the critical path.…”