An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment

Amla, Nina; Du, Xiaoqun; Kuehlmann, Andreas; Kurshan, Robert P.; McMillan, Kenneth L.

doi:10.1007/11560548_20

Cited by 69 publications

(52 citation statements)

References 31 publications

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“…This methodology is being introduced in validation methodology because not all the modules are well suited for simulations techniques. In [29], the authors presented the formal technique adopted by Brazil Semiconductor Technology Center (BSTC) which further divide into three additional techniques: model checking, theorem proving and equivalence checks. Model checking is an important technique for verifying sequential.…”

Section: Formal Verificationmentioning

confidence: 99%

RTL validation methodology on high complexity wireless microcontroller using OVM technique for fast time to market

et al. 2017

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Abstract. Increased demand in internet of thing (IOT) application based has inadvertently forced the move towards higher complexity of integrated circuit supporting SoC. Such spontaneous increased in complexity poses unequivocal complicated validation strategies. Hence, the complexity allows researchers to come out with various exceptional methodologies in order to overcome this problem. This in essence brings about the discovery of dynamic verification, formal verification and hybrid techniques. In reserve, it is very important to discover bugs at infancy of verification process in (SoC) in order to reduce time consuming and fast time to market for the system. Ergo, in this paper we are focusing on the methodology of verification that can be done at Register Transfer Level of SoC based on the AMBA bus design. On top of that, the discovery of others verification method called Open Verification Methodology (OVM) brings out an easier way in RTL validation methodology neither as the replacement for the traditional method yet as an effort for fast time to market for the system. Thus, the method called OVM is proposed in this paper as the verification method for larger design to avert the disclosure of the bottleneck in validation platform.

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Section: Formal Verificationmentioning

confidence: 99%

RTL validation methodology on high complexity wireless microcontroller using OVM technique for fast time to market

et al. 2017

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“…These algorithms can be broadly classified into three categories: (1) bounded model checking which is useful for finding failures (2) hybrid algorithms that combine SAT and BDD based methods for unbounded model checking, and (3) purely SAT-based unbounded model checking algorithms. Studies in this direction was carried out by Amla et al [10] who have describes eight bounded and unbounded techniques, and analyzes the performance of these algorithms on a large and diverse set of hardware benchmarks. Most recently, Mancini et al [11] showed how by combining Explicit Model Checking techniques and simulation it is possible to carry effectively out (bounded) System Level Formal Verification of large Hybrid Systems such as those defined using model-based tools like Simulink.…”

Section: Related Work Of Model Checkingmentioning

confidence: 99%

Research Trends in Formal Verification Process for Analog and Mixed Signal Design

S¹,

Manjunath²

2015

IJCA

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Formal verification is one of the crucial stages of design phase that ensure the preciseness of the circuit design and its corresponding behavior with respect to specific system design. From last decade, there has been an abundant formal verification techniques introduced by the research community for analog and mixed signal circuits that used as an interface between analog and digital components. Owing to the maximized sophistication, and shrinking sizes of chip, analog, and mixed signal verification is encountering challenges in increasing verification requirement that calls for analyzing the prior techniques. The prime purpose of this paper is to discuss the most standard models, and techniques introduced till date and to excavate the various facts about their effectiveness in the area circuit design principles. The paper also discusses some of the critical research gaps explored from the study.

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“…Embedded memories give rise to an exponential increase in the state-space of a design, dramatically increasing the verification and debugging complexity of the system. This compounds the statespace explosion problem which already limits the practical application of many verification tools [2], [3].…”

Section: Introductionmentioning

confidence: 99%

A succinct memory model for automated design debugging

Keng¹,

Mangassarian²,

Veneris³

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-In today's complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to the difficulty of the problem by exponentially increasing the statespace of the design. In this work, a novel memory model for design debugging is presented. It models memory succinctly by avoiding an explicit representation for each memory bit. The method uses the simulation of the erroneous design to guide the debugging process. This results in a parameterizable formal encoding that grows linearly with the erroneous trace length, significantly reducing the memory requirements of the debugging problem. In addition, the proposed model is extended to handle an arbitrary initial memory configuration, as well as non-cycle accurate output traces where only a final expected memory state is available for comparison. Experiments on industrial designs show a 96% average reduction in memory usage along with a noticeable performance improvement compared to previous work.

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An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment

Cited by 69 publications

References 31 publications

RTL validation methodology on high complexity wireless microcontroller using OVM technique for fast time to market

RTL validation methodology on high complexity wireless microcontroller using OVM technique for fast time to market

Research Trends in Formal Verification Process for Analog and Mixed Signal Design

A succinct memory model for automated design debugging

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