An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications

Enz, Christian; Krummenacher, F.; Vittoz, E.A.

doi:10.1007/978-1-4615-2283-6_7

Cited by 154 publications

(115 citation statements)

References 12 publications

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“…This makes this model especially suitable for transistor mismatch characterization. We have verified that very similar results are obtained if the EKV model [5] is used.…”

Section: Mismatch Modelsupporting

confidence: 80%

“…To generate a unique mismatch model valid in all regions of operation, a transistor model continuos from weak to strong inversion is necessary [5]- [6]. The present mismatch model is based on the ACM transistor model which is continuos for all regions of operations and is physically based, so that it has a reduced number of physically meaningful parameters [6].…”

Section: Mismatch Modelmentioning

confidence: 99%

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CMOS transistor mismatch model valid from weak to strong inversion

Serrano-Gotarredona

Linares-Barranco

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)

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“…This makes this model especially suitable for transistor mismatch characterization. We have verified that very similar results are obtained if the EKV model [5] is used.…”

Section: Mismatch Modelsupporting

confidence: 80%

Section: Mismatch Modelmentioning

confidence: 99%

CMOS transistor mismatch model valid from weak to strong inversion

Serrano-Gotarredona

Linares-Barranco

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)

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“…(m is the carrier mobility, C ox the gate oxide capacitance per unit area, W the width of the device, V T0 the threshold voltage of PMOS device, n p the subthreshold factor for PMOS device, and L e the effective device length) [5]. This expression indicates that I SD will increase with increasing V SD in this configuration and the slope factor would be (n À 1)=n p .…”

Section: Fig 1 MCML Buffer Stage and Its Dc Transfer Characteristicsmentioning

confidence: 98%

“…2 (inset) shows the proposed connection of the load device that can be used as a high resistance element where the body (n-well) terminal is connected to drain. Based on the EKV model [5], the I-V characteristics of this device can be expressed as: …”

Section: Fig 1 MCML Buffer Stage and Its Dc Transfer Characteristicsmentioning

confidence: 99%

Ultra-low power subthreshold current-mode logic utilising PMOS load device

et al. 2007

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A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18 mm CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1 nA, achieving sufficiently high gain ( > 3) over a wide frequency range.Introduction: Current-mode logic (CML) circuits are widely used in many high-speed and high-performance applications [1]. The differential topology of CML circuits provides high immunity to supply noise and crosstalk, while reduced voltage swing at the output helps to operate the circuit in very high frequencies with low noise generation [1,2]. These properties make the MOS CML (MCML) topology an attractive candidate for ultra-low power applications as well. This, however, usually requires that the circuit be biased in the subthreshold region, conducting a very low tail current and still producing a sufficiently large output swing. While several techniques for implementing CMOS logic circuits with transistors in the subthreshold regime and with very low power dissipation have been already introduced [3], the design of ultra-low power MCML circuits is yet an open research subject. This Letter introduces a new approach for implementing MCML circuits that can be applied to digital CMOS technologies.

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“…Thus, by increasing V SD , the threshold voltage of this device is modified, and consequently, the drain current will increase. This dependence of the current on drain voltage results in a large and finite output conductance that can be expressed as follows, based on the EKV model [5]:…”

mentioning

confidence: 99%

Implementing ultra-high-value floating tunable CMOS resistors

2008

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A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 mm CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-lowcutoff-frequency MOSFET-C filter.Introduction: Integrated high-value resistors (HVR) are key elements in many applications. Compact HVRs can be applied for biasing purposes or for implementing very-low-frequency filters [1,2]. In addition to achieving high resistance, usually it is necessary to have good tuning capability of the resistor value, thus the controllability of the HVR is another important design issue. In this Letter, a compact HVR is introduced that utilises only PMOS transistors operating in the subthreshold regime. The resistance is adjustable in a very wide range. This property makes this technique very suitable for ultra-low-power reconfigurable applications. A test chip has been fabricated in conventional 0.18 mm CMOS technology and characterised to verify this concept. The proposed HVR has been applied to implement a low-frequency MOSFET-C filter with a wide tuning range and a constant dynamic range (DR).

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An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications

Cited by 154 publications

References 12 publications

CMOS transistor mismatch model valid from weak to strong inversion

CMOS transistor mismatch model valid from weak to strong inversion

Ultra-low power subthreshold current-mode logic utilising PMOS load device

Implementing ultra-high-value floating tunable CMOS resistors

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