Ultra-low power subthreshold current-mode logic utilising PMOS load device

Abstract

A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18 mm CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1 nA, achieving sufficiently high gain ( > 3) over a wide frequency range.Introduction: Current-mode logic (CML) circuits are widely used in many high-speed and high-performance applications [1]. The differential topology of CML circuits provides high immunity to supply noise and crosstalk, while reduced voltage swing at the output helps to operate the circuit in very high frequencies with low noise generation [1,2]. These properties make the MOS CML (MCML) topology an attractive candidate for ultra-low power applications as well. This, however, usually requires that the circuit be biased in the subthreshold region, conducting a very low tail current and still producing a sufficiently large output swing. While several techniques for implementing CMOS logic circuits with transistors in the subthreshold regime and with very low power dissipation have been already introduced [3], the design of ultra-low power MCML circuits is yet an open research subject. This Letter introduces a new approach for implementing MCML circuits that can be applied to digital CMOS technologies.

Subthreshold leakage reduction: A comparative study of SCL and CMOS design

“…In this Section, after a short overview on source-coupled logic (SCL) and subthreshold SCL (STSCL) circuits [4], the main constraint in the design of STSCL circuits operating with ultra-low power consumption will be studied [5].…”

“…STSCL Topology Figure 1 shows the topology of a subthreshold SCL circuit [4]. In this topology, all transistors are biased in subthreshold regime.…”

“…Recently, subthreshold source-coupled logic (STSCL) circuits have been proposed for implementing ultra-low power applications [4], [5]. The proposed topology is based on a differential NMOS switching network performing the logic operation and also very compact and high value load resistances.…”

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

“…The design of such high-precision supply voltage control systems, however, becomes more challenging in battery operated systems where the power budget is very restricted and also battery voltage reduces with time. Subthreshold source-coupled logic (STSCL) topology has recently been shown as an alternative approach for implementing ultra-low power circuits [8], [9]. The accurate control on the power consumption of each gate makes this topology very suitable for very low bias current operations where the dissipation of conventional static CMOS circuits is limited by their subthreshold leakage current.…”

Implementing ultra-high-value floating tunable CMOS resistors

“…Fig. 1 (inset) shows the proposed device in which the transistor is biased in the subthreshold regime [3,4]. In this configuration, the bulk of the PMOS device (which is an isolated n-well) is connected to its drain.…”