An Application-Specific Design Methodology for On-Chip Crossbar Generation

Abstract

Abstract-Designing a power-efficient interconnection architecture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effectively handle the design complexity, it is essential to provide a computer-aided design tool support for automating this task. In this paper, we address the issue of "application-specific design of optimal crossbar architecture" satisfying the performance requirements of the application and optimal binding of the cores onto the crossbar resources. We present a simulation-based design approach that is based on the analysis of the actual traffic trace of the application, considering local variations in traffic rates, temporal overlap among traffic streams, and criticality of traffic streams. Our approach is physical design aware, where the wiring complexity of the crossbar architecture is also considered during the design process. This leads to detecting timing violations on the wires early in the design cycle and to having accurate estimates of the power consumption on the wires. We apply our methodology onto several MPSoC designs, and the synthesized crossbar platforms are validated for performance by cycle-accurate SystemC simulation of the designs. The crossbar matrix power consumption values are based on the synthesis of the register transfer level models of the designs, obtained using industry standard tools. The experimental case studies show large reduction in communication architecture power consumption (45.3% on average) and total wirelength (38% on average) for the MPSoC designs when compared with traditional design approaches. The synthesized crossbar designs also lead to large reduction in transaction latencies (up to 7×) when compared with the existing design approaches.

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

“…In recent years, some efficient interconnect architectures dedicated for a hardware fabric have been proposed to exploit the advantages of the fabric such as DESA NoC [Roca et al, 2012] or low-cost and specific-application crossbar in [Hur et al, 2012;Murali et al, 2007] developed for FPGAs. Additionally, many hybrid interconnects both in mixed NoC topologies and in mixed architectures have been proposed to improve the hybrid interconnect throughput or reduce hardware cost as presented in Section 2.2.…”

“…An n×n crossbar can quickly become prohibitively expensive as its cost increases by n 2 . To reduce the cost, many studies focusing on application-specific crossbars have been reported such as in [Hur et al, 2007], [Murali et al, 2007].…”

Architecture exploration of NAND flash-based multimedia card

“…Researches on bus matrix have tried to find out optimal bus matrix architectures considering the number of buses and arbitration schemes [3] [4]. However, these works focusing on on-chip communication architectures have paid no attention to low-level details of memory subsystem as considered in this paper.…”

“…Previous works on the design space exploration of communication architecture have mainly focused on the high performance embedded systems of increasing complexity [1][2][3] [4]. Since the performance is of primary concern, architecture exploration has been performed with the abstracted models of communication and memory system, based on approximate cost models.…”

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

“…To overcome the IP integration problem, earlier work mainly focused on static bridge designs [44,75]. Since the static approaches are inherently non-scalable and limited in the ability to provide high performance in cases where the traffic characteristics vary dynamically, a number of automatic designs were proposed to dynamically optimize the bus-based architectural topology [98,52,151]. Moreover, several design methodologies and design flow for customizing these architectures to adapt to traffic characteristics have further been studied [79,48,191].…”