An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

Sarma, Kaushik Chandra Deva; Sharma, Sweta

doi:10.1007/s10825-015-0700-6

Cited by 20 publications

(11 citation statements)

References 17 publications

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“…The FET is p-type doped with doping density considered for testing are 3.32 10  cm -2 and is taken as uniform throughout the entire device regions. Since BP exhibits high anisotropic carrier mobility with crystal orientation, we take only armchair direction (AC) as transport direction (as the current along the armchair direction is eight orders of magnitude larger than that in the zigzag (ZZ) direction for ML BP) [19][20][21], to achieve optimum performance. We employ the NEGF formalism to estimate the ballistic quantum transport properties of the device.…”

Section: Methodsmentioning

confidence: 99%

“…Additionally, due to its relatively small band gap, BP can be tuned into both p-type and n-type configurations in contrast to few-layer MoS2 which usually exhibits n-type behavior [13]. The phosphorus atoms of BP covalently bond to three neighbouring atoms but unlike graphene BP forms a puckered structure with out of plane ridges [15][16]. Individual layers of phosphorus atoms are held together by weak van der Waals forces [2,4].…”

Section: Introductionmentioning

confidence: 99%

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Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Sanda

Dey²,

Dhar

2023

Preprint

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Two-dimensional materials are very promising for ultra-short channel future devices. This paper investigates, for the first time, the viability of the junction less transistors based on 2-D materials for future state-of-the-art technology nodes. Specifically, we investigate the performance of a Junction less monolayer black phosphorus (BP) FET (JLFET) with 12nm gate length using ab initio quantum transport simulations. The electrostatic control mechanism of the device and various intrinsic static and dynamic characteristics of the device are studied. The results reveal that BP JLFET performance can fulfill the benchmark requirement of International Roadmap for Devices and Systems (IRDS 2021) for 2028 in terms of HP and HD applications. Therefore, JLFET based on 2D materials can be a promising alternative for nano scale future device applications.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Sanda

Dey²,

Dhar

2023

Preprint

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“…In 2022 Mendiratta et al 64 proposed the surface potential for the asymmetrical JL-dopingless DG FET by solving 2D Poisson's equation. This model was validated by plotting all the results on MATLAB and were compared with the results resulting from the TCAD tool.…”

Section: Ecs Journal Of Solid State Science and Technology 2023 12 03...mentioning

confidence: 99%

“…Total surface potential developed by them was 64 : The potential of the TMSED-GAA-MOSFET can be approximated using the Superposition Technique 66,67 and the usual Two-D Poisson's equation. Subthreshold current (I sub ) for the device has been formulated as 65…”

Section: Ecs Journal Of Solid State Science and Technology 2023 12 03...mentioning

confidence: 99%

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Raut¹,

Nanda²,

Panda³

2023

ECS J. Solid State Sci. Technol.

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Junction-less field effect transistors, also known as JLFETs, are widely regarded as the most promising candidate to replace the conventional metal oxide semiconductor field effect transistors (MOSFETs) currently used in integrated circuit technology. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold slope and drain induced barrier lowering (DIBL). Due to its gate coupling, the gate-all-around (GAA) JLFET is a better contender to uphold Moore's law than other existing device architectures and regular JLFET, allowing more precise channel tuning. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, no comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters have been provided in a single resource. From device evaluation and application to qualitative and quantitative parameter analysis studies likewise subthreshold swing, DIBL and switching ratio, this review provides comprehensive information on the various structures of Junctionless and GAA JLFETs. Furthermore, various device modeling techniques of JLFETs for enhancing the device's characteristics and its application in various semiconductor industries are provided.

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“…To overcome the fabrication difficulty to maintain very steep junctions at low dimensions, recently, an alternate MOS structure named Junctionless transistor was proposed [1]. Several analytical models were developed for double gate junctionless transistor with symmetric gate, assymetric gates [2][3][4][5][6]. The quantum confinements models are also available in literature for these structures [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

Bora

2021

Silicon

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This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

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An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

Cited by 20 publications

References 17 publications

Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

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