An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test

Basu, Anupam; Wilson, T.C.; Banerji, D.; Majithia, J.C.

doi:10.1109/icvd.1992.658084

“…An early structural-based BIST hardware synthesis algorithm at RTL was presented in [17] without taking into account the test application time. Another structuralbased BIST hardware synthesis algorithm that minimizes test application time and BIST area overhead was proposed in [18]. The algorithm, however, has an inefficient testable design space exploration due to fixed test resource allocation, which means that the test hardware is allocated before the test scheduling process.…”

Section: Previous Workmentioning

confidence: 99%

“…The previous approaches [24][25][26][27][28][29] proposed separate solutions for solving only one of the problems (a) -(c) at the expense of the other problems of the BIST embedding methodology. Furthermore, the interrelation between test synthesis and test scheduling which leads to huge size of the testable design space (problem d) was not solved efficiently by the previously described approaches [17][18][19][20][21][22] which trade-off the quality of the final solution and computational time.…”

Section: Motivation and Objectivesmentioning

confidence: 99%

BIST hardware synthesis for RTL data paths based on test compatibility classes

Nicolici

¹

,

Al-Hashimi

²

,

Brown

³

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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New BIST methodology for RTL data paths is presented. The proposed BIST methodology takes advantage of the structural information of RTL data path and reduces the test application time by grouping same-type modules into test compatibility classes (TCCs). During testing, compatible modules share a small number of test pattern generators at the same test time leading to significant reductions in BIST area overhead, performance degradation and test application time. Module output responses from each TCC are checked by comparators leading to substantial reduction in fault-escape probability. Only a single signature analysis register is required to compress the responses of each TCC which leads to high reductions in volume of output data and overall test application time (the sum of test application time and shifting time required to shift out test responses). This paper shows how the proposed TCC grouping methodology is a general case of the traditional BIST embedding methodology for RTL data paths with both uniform and variable bit width. A new BIST hardware synthesis algorithm employs efficient tabu search-based testable design space exploration which combines the accuracy of incremental test scheduling algorithms and the exploration speed of test scheduling algorithms based on fixed test resource allocation. To illustrate TCC grouping methodology efficiency, various benchmark and complex hypothetical data paths have been evaluated and significant improvements over BIST embedding methodology are achieved.

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“…The n-input k-bit comparator logic can be tested by a short deterministic test set, in the same way as multiplexers. It should be noted when n mod = n res the proposed BIST methodology is identical with the BIST embedding methodology [3,4,5] where each module is embedded between two test pattern generators and a signature analysis register. To illustrate the efficiency of RTL data path testing using TCCs consider the data path example of Figure 1, where LFSR 1 , LFSR 2 and LFSR 3 test three modules of A type , LFSR 4 , LFSR 5 and LFSR 6 test three modules of B type .…”

Section: Preliminary Definitionsmentioning

confidence: 99%

“…This approach does not take into account the test application time. A latter approach that minimizes test application time and area overhead is presented in [4]. The number of test plans examined for each module was limited to four which leads to inefficient testable design space exploration.…”

Section: Introductionmentioning

confidence: 99%

Efficient BIST hardware insertion with low test application time for synthesized data paths

Nicolici

¹

,

Al-Hashimi

²

1999

Proceedings of the Conference on Design, Automation and Test in Europe

2

0

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In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST environment. Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility classes and n-input k-bit comparators are used to check the results. The test application time is computed using an incremental test scheduling approach. An existing test scheduling algorithm is modified to obtain an efficient trade-off between the algorithm complexity and testable design space exploration. A cost function based on both test application time and area overhead is defined and a tabu search-based heuristic capable of exploring the solution space in a very rapid time is presented. To reduce the computational time testable design space exploration is carried out in two phases: test application time reduction phase and BIST area reduction phase. Experimental results are included confirming the efficiency of the proposed methodology.

show abstract

“…The n-input k-bit comparator logic can be tested by a short deterministic test set, in the same way as multiplexers. It should be noted when n mod = n res the proposed BIST methodology is identical with the BIST embedding methodology [3,4,5] where each module is embedded between two test pattern generators and a signature analysis register.…”

Section: Preliminary Definitionsmentioning

confidence: 99%

Efficient BIST hardware insertion with low test application time for synthesized data paths

Nicolici¹,

Al-Hashimi²

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

1

0

View full text Add to dashboard Cite

In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST environment. Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility classes and n-input k-bit comparators are used to check the results. The test application time is computed using an incremental test scheduling approach. An existing test scheduling algorithm is modified to obtain an efficient trade-off between the algorithm complexity and testable design space exploration. A cost function based on both test application time and area overhead is defined and a tabu search-based heuristic capable of exploring the solution space in a very rapid time is presented. To reduce the computational time testable design space exploration is carried out in two phases: test application time reduction phase and BIST area reduction phase. Experimental results are included confirming the efficiency of the proposed methodology.

show abstract

An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test

Cited by 6 publications

References 4 publications

BIST hardware synthesis for RTL data paths based on test compatibility classes

BIST hardware synthesis for RTL data paths based on test compatibility classes

Efficient BIST hardware insertion with low test application time for synthesized data paths

Efficient BIST hardware insertion with low test application time for synthesized data paths

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