No abstract

This paper presents a new test scheduling algorithm based on a new heuristic approach. A new concept of Time Zone Tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with the existing algorithms and at demonstrates encouraging results.

No abstract

OverviewMultiport memories can significantly reduce circuit complexity by allowing registers residing in the same memory t o share common d a t a paths between the memories and functional units. An earlier paper [1] described the advantages of using multiport memories in data path synthesis and provided a linear programming approach t o determine the maximum number of registers to place in a multiport memory with given port capabilit,ies However, t h a t paper considered allocation t o only one memory at a time and assumed the particular configuration of memories was totally prescribed by the designer.Here we extend that approach in various ways. We assign registers simultaneously t o a configuration of several memories; this gives a more uniform distribution of register activity across the memories and usually provides a more compact assignment, allowing even fewer ports and fewer module interconnections. We first extend the L.P. model and then present a fast heuristic approach that searches for an allocation. This allocation algorithm is part of a more general design tool that generates alternative multiport memory configurations and allows their rapid exploration. T h e designer specifies a range of design parameters and can control the thoroughness of the search. Within the limits set by the designer, the program finds the minimum cost configuration having a feasible register allocation. After describing the components of this system, we present some examples of its use. The Memory Allocation ProblemA memory configuration consists of a certain number of memories, each having a specific storage capacity and number of ports. T h e ports can have three functionalities: read-only; writeonly; and read/write. Given a particular memory configuration, the memory allocation problem consists finding some allocation of registers t o these memory modules that guarantees access on every control step t o all the registers participating in that control step..4llocating registers t o multiport memories is just one step in a sequence of steps t h a t converts a behavioral-level description of a circuit into a specification for the interconnection of functional units and storage elements. Clearly, detailed knowledge of register usage is needed in order t o determine which registers are active during the same control steps. Thus, register packing must follow the identification and minimization of registers, the association of prescribed operators with functional units, and the scheduling of operations in specific control steps. Data paths can be identified and routed only after the allocation of registers t o memories.Due t o often complex patterns of mutual register activity, a particular memory configuration may have no consistent packing, even if enough storage is available and enough ports appear t o be provided. On the other hand, any tw8.1 consistent allocation schemes are considered equivalent in terms of the packing problem. Although different register allocations tend to yield different module interconnection patterns,...

We present a n optimum and integrated solution t o the problems of scheduling, allocation, and binding using a n integer linear program (UP) that minimizes a weighted s u m of module area and total ezecution time under very general assumptions of module capability. T w o important eztensions are the use of pipelined functional units and operator chaining. The version of the ILP presented accelerates the solution in various ways.