An approximated soft error analysis technique for gate-level designs

Abstract

As the semi-conductor technology advances, the evaluation of soft error hardness for modern electrical and electronic devices becomes more generalized. Related studies have mainly focused on the soft error rate analysis of both combinational and sequential logic circuits, which includes techniques for dynamic simulation, and pathbased statistical estimation. In particular, non-dynamic approaches make the entire framework simple and compact. However, when the design under test has a large number of propagation paths, there is still a problem of increasing time complexity. This paper introduces an approximated soft error analysis technique, which constructs lookup tables with which to estimate transient pulses at the primary outputs. The whole process can be finished in polynomial time complexity. We employ node conditional probability to calculate the logical propagation probabilities without using static probability. The experimental results show that compared to the full-path analysis, the approximated technique can speed up the analysis time by 300% while the corresponding error rates for the evaluation results that are obtained are within 16% difference.

Cascaded Propagation and Reduction Techniques for Fault Binary Decision Diagram in Single-event Transient Analysis

“…Note that fBDD 2 is not on the re-convergent fan-out of the circuit since virtual PIs alone cannot exactly define the BDD in later converging logic gates without using the original PIs of fBDD 2 , which are already eliminated by the virtual PIs. This also agrees with the previous result where a combination of two input values in the logic gate of fan-in number two is sufficient for SER calculation when located on the non-re-convergent fanout [7]. Without loss of generality, fBDD j not on the reconvergent path where non-terminal vertices belong to {PI j , FF j } can be replaced by fBDD j with a virtual input VI j if two fBDD j and fBDD m are synthesized by the Boolean operation where {PI j , FF j }∩{PI m , FF m }=AE.…”

“…The parallelized method based on BDD [16] in our previous work involved individual SET analysis separated into multiple threads. The static propagation method is a non-BDD analysis but the individual propagation paths are mostly regarded as independent events [7,10]. This method was implemented by tool command language (TCL) running on the commercial static time analysis tool.…”

“…Path-based analysis techniques [4][5][6][7][8]10] employ static probabilities for circuit nodes, which are events that are independent of or less correlated with the other nodes. These are efficient and fast methods to estimate the SERs of typical combinational circuits.…”

“…To extract the specific SET instance for q and C L , two-dimensional interpolation will be conducted. During the SER analysis, electrical attenuation by a logic cell delay was estimated using existing techniques [7,10]. This paper focused on evaluating sea-level SER for the logic circuit.…”

“…Transient waveforms propagated along the circuit paths might be stored in the sequential element in the circuit and appear as soft errors. There have been numerous works [4][5][6][7][8][9][10][11][12] on the estimation of SERs caused by SETs in a static procedure. Symbolic framework using a binary decision diagram (BDD) provides a natural view that simultaneously considers electrical, logical, and timing propagation properties [11,12,18].…”