An architecture for electrically configurable gate arrays

Gamal, Abbas El; Greene, Jonathan; Reyneri, J.; Rogoyski, E.; El-Ayat, Khaled; Mohsen, A.M.

doi:10.1109/cicc.1988.20873

Cited by 18 publications

(14 citation statements)

References 3 publications

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“…The only alternative to this kind of empirical approach is the use of a theoretical approach in which applications are modeled in a statistical/graph-theoretical way, and the mapping of an application onto an architecture is modeled through a probabilistic calculation or through other theoretical machinery. While there have been a number of attempts to do this [44,52,78,79,91,159,244] these studies have necessarily focused on a fairly narrow spectrum of architectures and tools. They have typically been used to study routing architecture, rather than logic block architecture.…”

Section: Methodsmentioning

confidence: 99%

“…These blocks used a multiplexer as a basic logic element [79]. A configuration of three 2-to-1 multiplexers whose inputs were connected to constants or input signals, was used to provide a wide variety of logical functions.…”

Section: Commercial Logic Blocksmentioning

confidence: 99%

“…FPGA architects over the last two decades have selected basic logic blocks made of transistors (noted above) [144], NAND gates [160], an interconnection of multiplexers [79], lookup tables [49], and PAL-style wide-input gates [217]. These choices were originally driven by intuitive insights on the part of architects, typically with very little data or analysis, with a few exceptions [79]. In this survey, we discuss how the research foundations for choosing a logic block were established, and then focus on the effect of logic block functionality on the three key metrics: area, speed, and power.…”

Section: Fpga Logic Block Fundamentals and Trade-offsmentioning

confidence: 99%

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FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

331

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Section: Methodsmentioning

confidence: 99%

Section: Commercial Logic Blocksmentioning

confidence: 99%

Section: Fpga Logic Block Fundamentals and Trade-offsmentioning

confidence: 99%

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FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

331

109

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“…The FPGA segmented channel architecture was introduced by Gamal et al in [7]. Green et al formulated the FPGA segmented channel routing problem (FSCRP) in [7,8,19] and proved that it is NP-complete. Further work about the NP-completeness of the FSCRP was carried out by Li in [16].…”

Section: Introductionmentioning

confidence: 99%

“…Among the different types of existing FPGA architectures, one of the most studied is the row-based segmented channel routing model [4,7,8,11,16,18,19]. This architecture consists of rows of logic cells and routing channels.…”

Section: Introductionmentioning

confidence: 99%

Meta-Heuristic Algorithms for FPGA Segmented Channel Routing Problems with Non-standard Cost Functions

Salcedo‐Sanz

Yao

2005

Genet Program Evolvable Mach

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Abstract. In this paper we present three meta-heuristic approaches for FPGA segmented channel routing problems (FSCRPs) with a new cost function in which the cost of each assignment is not known in advance, and the cost of a solution only can be obtained from entire feasible assignments. Previous approaches to FSCPs cannot be applied to this kind of cost functions, and meta-heuristics are a good option to tackle the problem. We present two hybrid algorithms which use a Hopfield neural network to solve the problem's constraints, mixed with a Genetic Algorithm (GA) and a Simulated Annealing (SA). The third approach is a GA which manages the problem's constraints with a penalty function. We provide a complete analysis of the three metaheuristics, by tested them in several FSCRP instances, and comparing their performance and suitability to solve the FSCRP.

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