An architecture for electrically configurable gate arrays

Gamal, Abbas El; Greene, Jonathan; Reyneri, J.; Rogoyski, E.; El-Ayat, Khaled; Mohsen, A.M.

doi:10.1109/4.18600

Cited by 144 publications

(32 citation statements)

References 2 publications

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“…where a 2 0 (See equation (4) in follows). If the constructed segmentation has less tracks than T (the prede- segments are not good for I-segment routing.…”

Section: -Segmentation Designmentioning

confidence: 99%

“…Figure 1 shows a set of nets { T Z I , T Z Z , R~} to be routed in two different segmented channels with two tracks each. Switches are located at each crossing of vertical and horizontal segments (cross switch) and also between pairs of adjacent horizontal segments in the same track (horizontal switch) [4]. A symbol 0 represents a horizontal switch and a @ represents a cross switch.…”

Section: Introductionmentioning

confidence: 99%

“…Notice that p , , is the probability that a net is in the range (A,-I, A,] with its left end in the column group ((i -l)aA,,ZaA,], and hence N ' p i , is the average number of nets falling into such category. The function S, computed by equation(3)is used in equation(4) to scale the number of tracks. Since n,, in general depends on the column position x, the segmentation so constructed may have "holes" (SeeFigure 3).…”

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confidence: 99%

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On channel segmentation design for row-based FPGAs

Zhu

Wong

1992

IEEE/ACM International Conference on Computer-Aided Design

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The channel segmentation design problem for row-based FPGAs is to design a segmented channel to maximize the probability of successful routing. In this paper, we present an algorithm which takes an arbitrary net distribution and an integer K (specifying the maximum number of segments allowed in routing a net) as inputs, and automatically generates a segmented channel which is most suitable for K-segment channel routing. Our algorithm was tested extensively over various net distributions. We also present a new algorithm for segmented channel routing based on reducing the problem t o the maximum independent set problem for undirected graphs.

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“…where a 2 0 (See equation (4) in follows). If the constructed segmentation has less tracks than T (the prede- segments are not good for I-segment routing.…”

Section: -Segmentation Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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On channel segmentation design for row-based FPGAs

Zhu

Wong

1992

IEEE/ACM International Conference on Computer-Aided Design

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“…FPGAs combine the advantages of both gate arrays (DiGiacomo, 1989) and programmable logic devices (PLDs) (Coli, 1989). They are similar to gate arrays in structure but can be field-programmed (Rose et al, 1990;Gamal et al, 1989;Rose and Brown, 1991). This paper is organized as follows.…”

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confidence: 99%

CAD TOOL FOR IMPLEMENTATION OF FUZZY CONTROLLERS ON FPGAs

Manzoul

Jayabharathi²

1994

Cybernetics and Systems

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“…This reduces the problem of vertical constraints since at most one terminal enters the channel at any given column. More details on the architecture for row-based FPGAs and the segmented channel model can be found in [3] and [5], respectively.…”

Section: Prior Workmentioning

confidence: 99%

Architecture and routability analysis for row-based FPGAs

Pedram¹,

Nobandegani²,

Preas³

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

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FPGAs combine the logic integration benefits of customVLSI with the design, production, and time-to-market advantages of standard logic ICs. One class of FPGAs has rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeledgate arrays or standard cells. This class has the flavor of traditional channeledgate arrays or standard cells and is exemplified by the Actel family of FPGAs. However, unlike conventional standard cell designs, the FPGA routing channels contain predefined wiring segments of various lengths which may be anterconnected using antifuses. This paper develops analytical models that permit the design of FPGA routing channels and the analysis of the routability of row-based FPGAs devices based on a generic characterization of the row-based FPGA routing algorithms. I n particular, it demonstrates that (using probabilistic models for the origination point and length for connections) an FPGA with properly designed segment length and distribution can be nearly as eficient as a mask-programmable channel (in terms of number of tracks required for routing a given interconnection specification). Experimental results corroborate this prediction. In addition, this paper provides a method for evaluating various channel architectures.

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An architecture for electrically configurable gate arrays

Cited by 144 publications

References 2 publications

On channel segmentation design for row-based FPGAs

On channel segmentation design for row-based FPGAs

CAD TOOL FOR IMPLEMENTATION OF FUZZY CONTROLLERS ON FPGAs

Architecture and routability analysis for row-based FPGAs

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