Architecture and routability analysis for row-based FPGAs

Abstract

FPGAs combine the logic integration benefits of customVLSI with the design, production, and time-to-market advantages of standard logic ICs. One class of FPGAs has rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeledgate arrays or standard cells. This class has the flavor of traditional channeledgate arrays or standard cells and is exemplified by the Actel family of FPGAs. However, unlike conventional standard cell designs, the FPGA routing channels contain predefined wiring segments of various lengths which may be anterconnected using antifuses. This paper develops analytical models that permit the design of FPGA routing channels and the analysis of the routability of row-based FPGAs devices based on a generic characterization of the row-based FPGA routing algorithms. I n particular, it demonstrates that (using probabilistic models for the origination point and length for connections) an FPGA with properly designed segment length and distribution can be nearly as eficient as a mask-programmable channel (in terms of number of tracks required for routing a given interconnection specification). Experimental results corroborate this prediction. In addition, this paper provides a method for evaluating various channel architectures.

FPGA Architecture: Survey and Challenges

“…The only alternative to this kind of empirical approach is the use of a theoretical approach in which applications are modeled in a statistical/graph-theoretical way, and the mapping of an application onto an architecture is modeled through a probabilistic calculation or through other theoretical machinery. While there have been a number of attempts to do this [44,52,78,79,91,159,244] these studies have necessarily focused on a fairly narrow spectrum of architectures and tools. They have typically been used to study routing architecture, rather than logic block architecture.…”

FPGA Architecture: Survey and Challenges

“…The only alternative to this kind of empirical approach is the use of a theoretical approach in which applications are modeled in a statistical/graph-theoretical way, and the mapping of an application onto an architecture is modeled through a probabilistic calculation or through other theoretical machinery. While there have been a number of attempts to do this [44,52,78,79,91,159,244] these studies have necessarily focused on a fairly narrow spectrum of architectures and tools. They have typically been used to study routing architecture, rather than logic block architecture.…”

Channel segmentation design for symmetrical FPGAs

“…We assumed that the net left-end points follow a uniform distribution. (This choice bution for the net left-end point is very cl pirical studies [6] .) Moreroutability of the des e rate of successful r completion for random instances.…”