An Area and Power Efficient FFT Processor for UWB Systems

Qiao, Shushan; Hei, Yong; Wu, Bin; Zhou, Yumei

doi:10.1109/wicom.2007.151

Cited by 10 publications

(10 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…New area efficient and power efficient 128-point FFT processor has been designed for practical Ultra-Wideband (UWB) applications [2]. To develop and execute a 128-point FFT, the non-Cooley-Tukey radix-8 unit can be developed and implemented in this research work.…”

Section: Literature Surveymentioning

confidence: 99%

Low Power 128 Point Split Radix FFT for LTE Application

Shilpha¹

2014

IJMSR

View full text Add to dashboard Cite

-In this paper, we describe a processor architecture customized to Split radix FFT algorithm. The proposed architecture supports all FFT sizes, required by the LTE applications. The proposed design is aimed to reduce the area, latency, power and also to reduce the number of computational path in order to speed up FFT processor computation. The proposed low power 128 point split radix FFT architecture applies various periodicity properties of twiddle factors multiplier.We implement the processor in 128-point MDC architecture with split radix algorithm. The processor has been synthesized on a Xilinx ISE 10.1design technology and both energy-efficiency and performance have been evaluated.

show abstract

Section: Literature Surveymentioning

confidence: 99%

Low Power 128 Point Split Radix FFT for LTE Application

Shilpha¹

2014

IJMSR

View full text Add to dashboard Cite

show abstract

“…Common VLSI architectures of FFT can be classified into three categories: memory-based architectures [3,7,10,15,27,34,36], cached-memory architectures [2,24,29], and pipeline architectures [4,5,11,16,19,[21][22][23]25,28,31,32,35,37]. The memory-based architectures generally consist of a processing unit and a memory block.…”

Section: Introductionmentioning

confidence: 99%

A Low-Memory-Access Length-Adaptive Architecture for 2 $$^n$$ n -Point FFT

Chen

2014

Circuits Syst Signal Process

View full text Add to dashboard Cite

Fast Fourier transformation (FFT) is widely used in modern wireless communication and digital signal processing. Because memory access is a major cause of power dissipated by the long-length FFT architecture, this paper explores the design space expanded by FFT size and radix number in detail and presents a novel lowmemory-access length-adaptive architecture for computing any long-length 2 n -point FFT. The proposed hardware solution possesses the following three attractive features to reflect its novelty as compared to the existing designs. First, the authors identified that memory consumes major energy dissipation of a FFT processor and proposed to reduce memory access through decreasing the number of FFT butterfly stages. The second one is that we adopt the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware for computing variable-length FFT without sacrificing the hardware utilization as contrary to the feed-forward architecture. Finally, a 16-bank memory organization is proposed to achieve conflict-free FFT operations for various radixes. Such low-memory-access length-adaptive architecture can reduce almost 70 % memory access or 30 % power consumption for FFT computation. After being implemented through 1P6M TSMC 0.18-µm CMOS technology, this work costs a core area of only 4.49 mm 2 and meets the FFT real-time performance requirements of DVB-T2 systems when operated at 20 MHz frequency. The proposed design consumes only 1.44 nJ of energy per sample for computing FFTs. Through adopting the proposed low-memory-access algorithm, flexible length-adaptive architecture, and efficient 16-bank memory organization, 56 % power dissipation of the whole FFT chip can be saved.

show abstract

“…There are many works focusing on the FFT/IFFT processor. Y. W. Lin et al [3] proposes a mixed radix FFT algorithm by implementing radix-2 and radix-2 6 FFT. They divide the radix-2 6 FFT into two radix-2 3 FFT stages, and then realize the radix-2 3 FFT by 3 radix-2 stages.…”

Section: Introductionmentioning

confidence: 99%

“…Y. W. Lin et al [3] proposes a mixed radix FFT algorithm by implementing radix-2 and radix-2 6 FFT. They divide the radix-2 6 FFT into two radix-2 3 FFT stages, and then realize the radix-2 3 FFT by 3 radix-2 stages. The architecture is designed as four-parallel-paths SDF pipelines, the max work frequency of FFT chip reaches 250MHz under 180nm CMOS technology library, the throughput rate is 1G sample/s with power dissipation of 175mW.…”

Section: Introductionmentioning

confidence: 99%

“…Z.Wang et al [5] proposed a two-stage radix-2 2 and radix-32 FFT algorithm, it uses radix-2 5 algorithm instead of radix-32, four parallel pipelines are employed at the second stage. S.Qiao et al [6] Proposes radix-2 and radix-64 FFT algorithm as [3], however, it develops a non-Cooley-Tukey radix-8 unit in order to save hardware cost. The measurement result shows the throughput rate is 409.6M sample/s with area saved by 20% to 63% compared to that of radix-2 SDF architecture.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-power, high-speed FFT processor for MB-OFDM UWB application

Liang

Torre

et al. 2011

VLSI Circuits and Systems V

View full text Add to dashboard Cite

This paper presents a low-power, high-speed 4-data-path 128-point mixed-radix (radix-2 & radix-2 2 ) FFT processor for MB-OFDM Ultra-WideBand (UWB) systems. The processor employs the single-path delay feedback (SDF) pipelined structure for the proposed algorithm, it uses substructure-sharing multiplication units and shift-add structure other than traditional complex multipliers. Furthermore, the word lengths are properly chosen, thus the hardware costs and power consumption of the proposed FFT processor are efficiently reduced. The proposed FFT processor is verified and synthesized by using 0.13 µm CMOS technology with a supply voltage of 1.32 V. The implementation results indicate that the proposed 128-point mixed-radix FFT architecture supports a throughput rate of 1Gsample/s with lower power consumption in comparison to existing 128-point FFT architectures.

show abstract

An Area and Power Efficient FFT Processor for UWB Systems

Cited by 10 publications

References 7 publications

Low Power 128 Point Split Radix FFT for LTE Application

Low Power 128 Point Split Radix FFT for LTE Application

A Low-Memory-Access Length-Adaptive Architecture for 2 $$^n$$ n -Point FFT

Low-power, high-speed FFT processor for MB-OFDM UWB application

Contact Info

Product

Resources

About