This paper presents a novel 128-point Fast Fourier Transform (FFT) processor for practical Ultra-wideband (UWB) applications. The pipeline FFT processor based on the proposed non-Cooley-Tukey radix-8 unit can provide high throughput rate and has low hardware complexity. The radix-8 unit's hardware cost can save up to 20% compared with Radix-2 Single path Delay Feedback (R2SDF) architecture. Furthermore, both the input and output are in nature order. A 128-point FFT processor has been designed and implemented with SMIC 0.18µm CMOS process based on the proposed architecture. The throughput rate of proposed FFT processor is up to 409.6 Msample/s, which can meet the specification of UWB systems.

The design of 3 rd /5 th order active RC Chebyshev low-pass filter (LPF) with reconfigurable bandwidth and gain is based on 55 nm CMOS technology. The filter is integrated into draft IEEE 802.11ax concurrent dual band four antenna transceiver analog baseband circuit. Programmable capacitor bank of the filter is used to adjust bandwidth. The typical bandwidth of receiving filter is 10/20/40 MHz, and that of transmitting filter is 12/24/50 MHz. Adjust the gain ranging from -10 to 18 dB in passband by programmable resistor bank. The current consumption of typical bandwidth of receiving filter is 2.08 mA at a 1.5 V supply and has properties of 10 MHz bandwidth (BW), 36 dB gain, -62 dBm input signal, -39 dB third intermodulation distortion (IMD3), 17.1 nV/√Hz equivalent input noise (EIN). As for transmitting filter, the current consumption of typical bandwidth is 1.25 mA at a 1.5 V supply and has the properties of 10 MHz BW, -6 dB gain, 0 dBm input signal, -38 dB IMD3, 75 nV/√Hz EIN. Area of the whole filter is 0.08 mm 2 . INDEX TERMS Active RC, analog baseband, low-pass filter.

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Hardware implementation of LTE-Advanced systems using FPGA and ASIC technology is a highly promising technology. This article proposed a reliable and effective architecture for a LTE downlink transmitter under different antenna configurations including SISO 1×1; MIMO 2×2. The design has been synthesized using Altera Quartus II 13.1.4 on Altera Stratix-V 5SGSMD8K2F40I2. The parameter improving cost is introduced to evaluate the upgrading of resources caused by performance improvement. With this proposed structure, improving cost can be reduced compared with traditional method. The proposed plan is fabricated as an ASIC using SMIC 55-nm CMOS technology. Finally, the design is demonstrated in the test platform, showing a successful performance.