An area efficient 10-bit time mode hybrid DAC with current settling error compensation

Ravikumar, N.; Hoseini, Zaniar; Lee, Kye-Shin; Hariharan, S. I.; Lee, Yong Min

doi:10.1109/mwscas.2015.7282103

Cited by 4 publications

(1 citation statement)

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“…10-bit hybrid DAC reported by Ravikumar et al (2015) implemented equal number of bits from time-mode (MSB part) and current-steering (LSB part) architectures. With this configuration, the die area has been greatly reduced, i.e.…”

Section: Introductionmentioning

confidence: 99%

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Idros

Rosli

Aziz

et al. 2021

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Purpose The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures. Design/methodology/approach The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V. Findings Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm2 DAC consumed 12.6 mW for the data conversion. Originality/value This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

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Section: Introductionmentioning

confidence: 99%