Microelectronics Reliability
 2014
DOI: 10.1016/j.microrel.2013.12.004
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An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application

Jie Zeng
1
,
Dong Su
2
,
Liang‐Cai Zhong
3
et al.
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Cited by 8 publications
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References 11 publications
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Design, fabrication and test of novel LDMOS-SCR for improving holding voltage

Liu
1
,
Wang
2
,
Zhou
3
et al. 2015
Solid-State Electronics
9
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Design, fabrication and test of novel LDMOS-SCR for improving holding voltage

Liu
1
,
Wang
2
,
Zhou
3
et al. 2015
Solid-State Electronics
9
0
0
0
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Pickup impact on high-voltage multifinger LDMOS–SCR with low trigger voltage and high failure current

Liu
1
,
Jin
2
,
Wang
3
et al. 2015
Solid-State Electronics
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Investigating the trade-off between BV stability and ESD robustness in the n-channel LDMOS devices

Liang,
Li,
Liu
et al. 2024
Semicond. Sci. Technol.
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