An area efficient Q-format multiplier with high performance for digital processing applications

Rao, Vaddempudi Koteswara; Lavanya, K.

doi:10.1109/primeasia.2015.7450485

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2020

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“…As number of bits of addends increases, time to complete addition also increases, ultimately leading to decrease in throughput of the multiplier. DSPs and communication systems rely heavily on adders and multipliers for processing their data [4,5]. Existing multiplier systems consume more power and time and are thus, not suitable for DSP and communication systems [6].…”

Section: Introductionmentioning

confidence: 99%

Pipelined vedic multiplier with manifold adder complexity levels

Eshack¹,

Krishnakumar²

2020

IJECE

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Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is noticed that as complexity of adders in the multipliers reduce, the systems show improved speed and least hardware utilization. The architecture designed using 2 x 2 – bit pipelined Vedic multiplier is, then, compared with existing Vedic multipliers and conventional multipliers and shows least delay.

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Section: Introductionmentioning

confidence: 99%