An area-optimality study of floorplanning

Cong, Jason; Nataneli, Gabriele; Romesis, Michail; Shinnerl, Joseph R.

doi:10.1145/981066.981083

Cited by 18 publications

(15 citation statements)

References 17 publications

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“…They all cannot obtain desirable floorplans for the flip-chip design directly.) We shall also note that the B*-tree floorplanner is considered a leading tool in block floorplanning [6,10,20].…”

Section: Resultsmentioning

confidence: 99%

Simultaneous block and I/O buffer floorplanning for flip-chip design

Peng

Chang

Wang

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as well as the delay skew of the paths are simultaneously minimized. We then present a hierarchical method to solve the problem. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the alternating and interacting global optimization step and the partitioning step. The global optimization step places blocks based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the blocks are divided into two groups and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of blocks, defined by the ratio of the total block area to the chip area. At last, we refine the floorplan by perturbing blocks inside a subregion as well as in different subregions. Compared with the B*-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies.

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Section: Resultsmentioning

confidence: 99%

Simultaneous block and I/O buffer floorplanning for flip-chip design

Peng

Chang

Wang

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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“…PATOMA 1.0 [13] pioneered a top-down floorplanning framework that utilizes fast block-packing algorithms (ROB or ZDS [12]) and hypergraph partitioning with hMetis [20]. This approach is fast and scalable, and provides good solutions for many input configurations.…”

Section: Previous Workmentioning

confidence: 99%

Solving hard instances of floorplacement

Markov

Aggarwal

et al. 2006

Proceedings of the 2006 International Symposium on Physical Design

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Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, embedded memories and custom RTL blocks. At current and future technology nodes, their power and performance are impacted, more than ever, by the placement of their modules. However, our experiments show that traditional techniques for placement and floorplanning, and existing academic tools cannot reliably solve the placement task.To study this problem, we identify particularly difficult industrial instances and reproduce the failures of existing tools by modifying public-domain netlists. Furthermore, we propose algorithms that facilitate floorplacement of these difficult instances. Empirically, our techniques consistently produced legal placements, and on instances where comparison is possible, reduced wirelength by 3.5% over Capo 9.4 and 14.5% over PATOMA 1.0 -the pre-existing tools that most frequently produced legal placements in our experiments.

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“…To this end, [5] evaluates the sub-optimality of existing floorplanners by constructing benchmarks with zero dead-space. However, most realistic examples with hard blocks cannot be packed without dead-space, so an optimal block-packer allows one to use more realistic benchmarks for evaluating sub-optimality.…”

Section: Introductionmentioning

confidence: 99%

“…BloBB's extension for soft blocks is able to pack the soft versions of all MCNC benchmarks, except for apte, and all GSRC benchmarks with zero dead-space. Hence, the benchmarks in [5] appear less attractive.…”

Section: Introductionmentioning

confidence: 99%

Practical slicing and non-slicing block-packing without simulated annealing

Chan

Markov

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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We propose a new floorplanner BloBB based on multi-level branch-andbound. It is competitive with annealers in terms of runtime and solution quality. We empirically quantify the gap between optimal slicing and non-slicing floorplans by comparing optimal packings and best seen results. Optimal slicing and non-slicing packings for apte, xerox and hp are reported. We also discover that the soft versions of all MCNC benchmarks, except for apte, and all GSRC benchmarks can be packed with zero dead-space.Additionally, realistic floorplans often have blocks with similar dimensions, if design blocks, such as memories, are reused. We show that this greatly reduces the complexity of black-packing.

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An area-optimality study of floorplanning

Cited by 18 publications

References 17 publications

Simultaneous block and I/O buffer floorplanning for flip-chip design

Simultaneous block and I/O buffer floorplanning for flip-chip design

Solving hard instances of floorplacement

Practical slicing and non-slicing block-packing without simulated annealing

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