Simultaneous block and I/O buffer floorplanning for flip-chip design

Abstract

The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as well as the delay skew of the paths are simultaneously minimized. We then present a hierarchical method to solve the problem. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the alternating and interacting global optimization step and the partitioning step. The global optimization step places blocks based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the blocks are divided into two groups and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of blocks, defined by the ratio of the total block area to the chip area. At last, we refine the floorplan by perturbing blocks inside a subregion as well as in different subregions. Compared with the B*-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies.

Area-I/O flip-chip routing for chip-package co-design

“…In Table I, "Circuits" gives the names of circuits, "#Blocks" gives the number of blocks, "#Ports" gives the number of block ports, "#Pads" gives the number of I/O pads, "#Balls" gives the number of bump pads, and "#RDLs" gives the number of redistribution layers. [6]. Two experiments were performed to test our router.…”

“…We used the benchmarks and the program presented in [6]. The benchmarks are from the industry and shown in Table III.…”

“…We assume that there is only one RDL for routing for this experiment. Given a netlist among block ports, I/O pads, and bump pads, the work [6] floorplans blocks and I/O buffers with fixed bump balls to minimize the total wirelength. First, each circuit was floorplanned by the program in the total wirelength minimization mode.…”

“…is the improvement of the total wirelength. Note that the wirelength reported in the column "ASPDAC-06" just gives the half-perimeter wirelength estimation in the RDL routing after the floorplanning by the work [6], while the wirelength reported in the column "Ours" is the final routed wirelength. Therefore, the numbers in the "ASPDAC-06" column just give a lower bound of the routed wirelength.…”

Package-chip co-design to increase flip-chip C4 reliability

“…There have been a few recent works that consider the flip chip packaging problem with some of these works focusing on C4 bump placement [4]. Others have focused on the co-optimization of the placement of I/O buffers, C4 bumps and blocks so as to minimize design metrics such as total wirelength and skew [5]- [7]. Others have considered flip chip routing and how it affects PCB escape routing [8].…”