Unified Padring Design Flow - New Developments and Results

Abstract

In the early design phase, padring design is one of the critical elements in design planning. The result from padring design not only will impact packaging, board level design, power integrity and signal integrity result, but also the overall product cost .In the past, padring design is often done through separate standalone tool like Orbit IO or internal excel estimation spreadsheet. The process of padring design is a tedious step as it involves a lot of hand editing and the quality of the padring placement rely on the experience of dedicated padring designer. The intend of this paper is to share the automated unified padring design methodology where single design database is referenced hence padring design will always be in sync with fullchip backend database. The automated unified padring flow allows consistent cross functional review reference point, better controllability for core and padring design integration and enhance the padring design process efficiency by minimizing the experience gap of the padring designer in charged. Hopefully the methodology proposed will benefit the padring designers in floorplanning and product cost estimation through unified padring flow.

Metadata based padring and pad multiplexing generation for microcontroller design

“…In the design of a microcontroller SoC (System on Chip), pads definition and their interconnections are one of the most time consuming and error prone step in the integration RTL (Register Transfer Logic) process [4] [5]. To achieve the specification of a design, the number of variables related to functionality that a specific pin will present reveals an extremely complex number of connections that needs to be made [6].…”

“…A fast and reliable design of padring code speeds up the integration cycle, reduces the cost of new SoCs [4] and decreases time to market of new designs [7]. There are two relevant aspects in padrings; one is the physical placement and organization [4] [5] [8] and the other is the logical perspective, which includes the functional and test pin multiplexing [8].…”