Defining padring and its pad interconnections is one of the most time consuming steps of a microcontroller SoC design. Also, multiple device features plus testability in limited pinout packages entails more functions shared per pin. As such, the number of padring connections and complexity exponentially grows at each new design. This paper describes a methodology to configure pad connections and select correct pad cells. The methodology works out technology and function definitions for each pin using new and previous designs data stored in a metadata database in order to generate the padring RTL code for the SoC. This methodology was proven with Freescale microcontrollers, among them to check the padring connection of the commercial microcontroller MC9S08MP16 [1], and was used to implement both MC9S08QB8 [2] and MC9S08SC4 [3] microcontrollers, which resulted in reduced design time in order of 10 folds, along with high quality generated RTLs.