An arnoldi based thermal network reduction method for electro-thermal analysis

Codecasa, Lorenzo; D'Amore, D.; Maffezzoni, P.

doi:10.1109/tcapt.2002.808005

Cited by 86 publications

(41 citation statements)

References 8 publications

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“…Grid-based methods can expediently handle complicated chip geometries of a ULSI chip, albeit requiring large amounts of grids for volume/surface meshing. Therefore, various sophisticated acceleration techniques were introduced in grid-based thermal-analysis methods, such as the Krylov-subspace-based model order reduction technique, the alternating direction implicit method, the adaptive meshing technique, and sparse-matrix algorithms [11]- [13]. In comparison to grid-based methods, Green's function-based thermal-analysis methods are advantageous in ULSI physical design algorithms such as floor planning and cell placement [14]- [16].…”

Section: Introductionmentioning

confidence: 99%

Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function

Wang

Mazumder

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Continual scaling of transistors and interconnects has exacerbated the power and thermal management problems in the design of ultralarge-scale integrated (ULSI) circuits. This paper presents an efficient thermal-analysis method of O(N lg N ) complexity, where N is the number of blocks that discretize the heat-source or temperature-observation regions. The method is named LOTAGre and formulated using the Green's function for heat conduction through multiple-layer materials, which account for the structure of ULSI chips and the accompanying heat sinks and mounting accessories. In addition to analyzing the thermal effects of the distributive heat sources, LOTAGre also considers the ambient temperature effects that are generally excluded in conventional Green's function-based thermal-analysis tools in order to avoid the concomitant analytical complexity. By employing the well-known eigen-expansion technique and classical transmissionline theory, fully analytical and explicit formulas are derived in this paper for the multilayer Green's function with the inclusion of the s-domain version, the homogeneous and inhomogeneous solutions to the heat-conduction equation. Then, the discrete cosine transform and its inversion are employed to accelerate the numerical computation of the homogeneous and inhomogeneous solutions. This paper includes extensive experimental results to demonstrate that LOTAGre can be as accurate as FLUENT, a sophisticated computational fluid dynamics tool, while speeding up the simulation run time by two to three orders of magnitude in comparison to FLUENT as well as conventional Green's functionbased thermal-analysis methods. This paper also discusses the limitations of using the traditional single-layer thermal model in thermal analysis for approximating a multilayer chip structure.

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Section: Introductionmentioning

confidence: 99%

Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function

Wang

Mazumder

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…These techniques have been succesfully demonstrated to work in a wide range of engineering fields including fluid dynamics [16], VLSI design [17], and control of fluid flow [18]. They have also been proposed in the MEMS and electronics packaging community [19], [20]. In [19], an Arnoldi-based thermal network has been proposed that gives very good results using a single reduced-order model for an entire device.…”

Section: Introductionmentioning

confidence: 99%

Interconnection of Subsystem Reduced-Order Models in the Electrothermal Analysis of Large Systems

Mathai

Shapiro

2007

IEEE Trans. Comp. Packag. Technol.

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Abstract-Heat conduction in an electronic device is commonly modeled as a discretized thermal system (eg, finite element or finite difference models) that typically uses large matrices for solving complex problems. The large size of electronic-system heat transfer models can be reduced using model reduction methods and the resulting reduced-order models can yield accurate results with far less computational costs. Electronic devices are typically composed of components, like chips, printed circuit boards, and heat sinks that are coupled together. There are two ways of creating reduced-order models for devices that have many coupled components. The first way is to create a single reduced-order model of the entire device. The second way is to interconnect reduced-order models of the components that constitute the device. The second choice (which we call the "reduce then interconnect" approach) allows the heat transfer specialist to perform quick simulations of different architectures of the device by using a library of reduced-order models of the different components that make up the device. However, interconnecting reduced-order models in a straightforward manner can result in unstable behavior. The purpose of this paper is two-fold: creating reduced-order models of the components using a Krylov subspace algorithm and interconnecting the reducedorder models in a stable manner using concepts from control theory. In this paper we explain the logic behind the "reduce then interconnect" approach, formulate a control-theoretic method for it, and finally exhibit the whole process numerically, by applying it to an example heat conduction problem.

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“…Starting from FEM models with MOR algorithms [35][36][37][38][39]. In this work, the Multipoint Moment Matching (MPMM) [35,36] MOR technique has been considered due to the following appealing features:…”

mentioning

confidence: 99%

“…In this work, the Multipoint Moment Matching (MPMM) [35,36] MOR technique has been considered due to the following appealing features:…”

mentioning

confidence: 99%

“…Equations (1)- (3) are to be coupled with suitable boundary conditions (thermal equilibrium with ambient is assumed at t = 0). The adopted MOR procedure is fully automatic and relies on MPMM [35,36], which involves the solution of the thermal problem in a frequency domain, i.e., of linear algebraic systems instead of ordinary differential equations. In particular, the problem is evaluated by fixing the frequency at specific values automatically evaluated according to a single user-defined error parameter [21].…”

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confidence: 99%

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On-Line Junction Temperature Monitoring of Switching Devices with Dynamic Compact Thermal Models Extracted with Model Order Reduction

et al. 2017

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Abstract:Residual lifetime estimation has gained a key point among the techniques that improve the reliability and the efficiency of power converters. The main cause of failures are the junction temperature cycles exhibited by switching devices during their normal operation; therefore, reliable power converter lifetime estimation requires the knowledge of the junction temperature time profile. Since on-line dynamic temperature measurements are extremely difficult, in this work an innovative real-time monitoring strategy is proposed, which is capable of estimating the junction temperature profile from the measurement of the dissipated powers through an accurate and compact thermal model of the whole power module. The equations of this model can be easily implemented inside a FPGA, exploiting the control architecture already present in modern power converters. Experimental results on an IGBT power module demonstrate the reliability of the proposed method.

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An arnoldi based thermal network reduction method for electro-thermal analysis

Cited by 86 publications

References 8 publications

Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function

Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function

Interconnection of Subsystem Reduced-Order Models in the Electrothermal Analysis of Large Systems

On-Line Junction Temperature Monitoring of Switching Devices with Dynamic Compact Thermal Models Extracted with Model Order Reduction

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