An ASIC perspective on FPGA optimizations

Ehliar, Andreas; Liu, Dake

doi:10.1109/fpl.2009.5272311

Cited by 15 publications

(8 citation statements)

References 3 publications

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“…Here, it has to be recalled that the RISPP architecture is envisioned to be an ASIC design with an embedded FPGA (like presented and analyzed in Neumann et al [NvSBN08] and Sydow et al [SNBN06]) and for prototyping purpose all parts are implemented on an FPGA. Ehliar cost for multiplexers, comparing FPGA targets with an ASIC target [EL09]. They compared the implementation cost for a 32-bit 16:1 multiplexer (MUX) with a 32-bit adder and presented the area requirements of the MUX relative to the adder requirements of the same technology.…”

Section: Rispp Prototype Implementation and Resultsmentioning

confidence: 99%

Run-time Adaptation for Reconfigurable Embedded Processors

Bauer¹,

Henkel

2011

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Section: Rispp Prototype Implementation and Resultsmentioning

confidence: 99%

Run-time Adaptation for Reconfigurable Embedded Processors

Bauer¹,

Henkel

2011

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“…FPGAs are quite comfortable for prototyping as done here but are quite inefficient in the matters of power consumption, area utilization, and operating frequency in comparison to ASICs. 57 − 59 Specifically, for example, according to ref ( 59 ), we can expect that for a full system design, the equivalent ASIC area will be up to 10 times smaller than the FPGA area. Therefore, we can expect that by having an ASIC of the same die size as the FPGA, we can potentially support up to 10,240 iterative mRNAs and 1280 parallel mRNAs.…”

Section: Discussionmentioning

confidence: 99%

Accelerating Whole-Cell Simulations of mRNA Translation Using a Dedicated Hardware

et al. 2021

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In recent years, intracellular biophysical simulations have been used with increasing frequency not only for answering basic scientific questions but also in the field of synthetic biology. However, since these models include networks of interaction between millions of components, they are extremely time-consuming and cannot run easily on parallel computers. In this study, we demonstrate for the first time a novel approach addressing this challenge by using a dedicated hardware designed specifically to simulate such processes. As a proof of concept, we specifically focus on mRNA translation, which is the process consuming most of the energy in the cell. We design a hardware that simulates translation in Escherichia coli and Saccharomyces cerevisiae for thousands of mRNAs and ribosomes, which is in orders of magnitude faster than a similar software solution. With the sharp increase in the amount of genomic data available today and the complexity of the corresponding models inferred from them, we believe that the strategy suggested here will become common and can be used among others for simulating entire cells with all gene expression steps.

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“…Here, it has to be recalled, that the RISPP architecture is envisioned to be an ASIC design with an embedded FPGA (like presented and analyzed in [NvSBN08,SNBN06]) and for prototyping purpose all parts are implemented on an FPGA. Ehliar and Liu analyzed the hardware implementation cost for multiplexers, comparing FPGA targets with an ASIC target [EL09]. They compared the implementation cost for a 32-bit 16:1 multiplexer (MUX) with a 32-bit adder and presented the area requirements of the MUX relative to the adder requirements of the same technology.…”

Section: Rispp Prototype Implementation and Resultsmentioning

confidence: 99%

RISPP: A run-time adaptive reconfigurable embedded processor

Bauer

Shafique

Henkel

2009

2009 International Conference on Field Programmable Logic and Applications

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Hiermit erkläre ich an Eides statt, dass ich die von mir vorgelegte Arbeit selbständig verfasst habe, dass ich die verwendeten Quellen, Internet-Quellen und Hilfsmittel vollständig angegeben habe und dass ich die Stellen der Arbeit -einschließlich Tabellen, Karten und Abbildungen -die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. ____________________________________ L a r s B a u e r i AcknowledgementsI want to thank my advisor Prof. Jörg Henkel for the inspirations, discussions, and opportunities he provided and shared with me. He managed to guide and to challenge me while giving me all freedom to follow my ideas and interests. Working with him was a nice experience and it definitely had a strong influence on my independent approach to work.I also want to thank all colleagues from the Chair for Embedded Systems for the nice discussions and the good time. In the last two month before submitting my thesis, especially Thomas Ebi and Sebastian Kobbe provided consistent support by helping me managing the daily workload and by sharing their coffee machines, which I cannot appreciate enough. Additionally, it is especially due to the secretaries and technicians that we can research in a good working environment and I explicitly want to acknowledge their work during all the time.Special thanks go to my colleague and room mate Muhammad Shafique. Without him, the work would not have been what it became. The technical discussions on application-and architecture-aspects improved the quality of this work more than once. I also want to thank the Master students that I supervised in the scope of this thesis.It was a nice experience to collaborate with colleagues from the groups (in alphabetical order) of Prof. AbstractReconfigurable embedded processors are a special class of processors comprising an extended instruction set that is implemented using a reconfigurable fabric. The instruction-set extension is typically application specific, but it is not required to finalize it when designing the processor. The reconfigurable fabric (e.g. a field-programmable gate array (FPGA)) allows that the accelerators that are used to implement the instruction-set extension may be reconfigured during run time without affecting the functionality of the working processor. Therefore, the accelerators -and thus the instruction-set extension -may be adapted according to the requirements of a running application.State-of-the-art reconfigurable processors require that the application programmer (or compiler) determines during compile time 'which' reconfigurations shall be performed and 'when' they shall be performed, i.e. which accelerators shall be loaded to a particular part of the reconfigurable fabric at a certain time. The problem is that it is typically not known during compile time which applications execute at the same time (i.e. in a multi-tasking environment), demanding the reconfigurable fabric. Additionally, it is not necessa...

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An ASIC perspective on FPGA optimizations

Cited by 15 publications

References 3 publications

Run-time Adaptation for Reconfigurable Embedded Processors

Run-time Adaptation for Reconfigurable Embedded Processors

Accelerating Whole-Cell Simulations of mRNA Translation Using a Dedicated Hardware

RISPP: A run-time adaptive reconfigurable embedded processor

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