An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency

Hinds, Michael; Sparkman, Brett; Di, Jia; Smith, Scott

doi:10.1166/jolpe.2013.1251

Cited by 2 publications

(1 citation statement)

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“…Multi-Threshold NULL Convention Logic (MTNCL) [7][8][9][10][11][12][13][14][15] is created by implementing MTCMOS power-gating in NCL. MTNCL uses both Low-V t and High-V t transistors and introduces a sleep function that replaces the functionality of hysteresis.…”

Section: Asynchronous Circuitsmentioning

confidence: 99%

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits

Suchanek

Zhong

2018

VLSICS

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Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a "stacked" architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of V DD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the "stacked" architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.

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Section: Asynchronous Circuitsmentioning

confidence: 99%

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits

Suchanek

Zhong

2018

VLSICS

Self Cite

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A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter

Moghaddam

Moaiyeri

Eshghi

et al. 2015

J CIRCUIT SYST COMP

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This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V DDL , V DDH ) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

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An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency

Cited by 2 publications

References 0 publications

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits

A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter

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