An asynchronous architecture for modeling intersegmental neural communication

Patel, G.R.; Reid, Michael S.; Schimmel, D.E.; DeWeerth, Stephen P.

doi:10.1109/tvlsi.2005.863762

Cited by 13 publications

(10 citation statements)

References 16 publications

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“…Massive and reconfigurable connectivity is implemented with fast, timemultiplexed, asynchronous digital circuits that communicate the spikes these silicon neurons emit [5,6]. They are often organized in two-dimensional (2D) arrays and serviced by a transceiver that reads spikes from and writes spikes to a row in parallel [7,8], an embedded memory that provides reconfigurable connectivity [9,10], and an on-chip router that communicates spike packets between chips [11,12] (Fig. 1a).…”

Section: Neuromorphic Networkmentioning

confidence: 99%

“…The router process provides four functions: (1) Accepts packets originating from its local spike transmitter or analogto-digital converter (ADC) 12 ; (2) Relays packets traveling up the tree from either of its daughters to its parent; (3) Relays packets traveling down the tree from its parent to either or both of its daughters; (4) Delivers packets that have reached their destination to one of two local memories; one stores synaptic connectivity, the other stores neuron parameters (see Appendix for details). To accomplish these tasks, it communicates with the transmitter and ADC on two input ports (Tx and ADC), with the daughters on two bi-directional ports (L i ,L o and R i ,R o ), with the parent on a third bidirectional port (T i ,T o ), 11 The design methodology is quasi (as opposed to fully) delay-insensitive because some circuits require wire branches to have smaller delays than gates-otherwise a race condition can occur.…”

Section: A Chp Specificationmentioning

confidence: 99%

“…In practice, it is relatively straightforward to ensure the physical design meets the required timing assumptions. 12 The ADC can measure the internal analog values of a subset of signals for any neuron in the chip, and convert them into packets that are sent off chip.…”

Section: A Chp Specificationmentioning

confidence: 99%

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A Multicast Tree Router for Multichip Neuromorphic Systems

Merolla

Arthur

Alvarez

et al. 2014

IEEE Trans. Circuits Syst. I

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Abstract-We present a tree router for multichip systems that guarantees deadlock-free multicast packet routing without dropping packets or restricting their length. Multicast routing is required to efficiently connect massively parallel systems' computational units when each unit is connected to thousands of others residing on multiple chips, which is the case in neuromorphic systems. Our tree router implements this one-tomany routing by branching recursively-broadcasting the packet within a specified subtree. Within this subtree, the packet is only accepted by chips that have been programmed to do so. This approach boosts throughput because memory look-ups are avoided enroute, and keeps the header compact because it only specifies the route to the subtree's root. Deadlock is avoided by routing in two phases-an upward phase and a downward phase-and by restricting branching to the downward phase. This design is the first fully implemented wormhole router with packet-branching that can never deadlock. The design's effectiveness is demonstrated in Neurogrid, a million-neuron neuromorphic system consisting of sixteen chips. Each chip has a 256×256 silicon-neuron array integrated with a full-custom asynchronous VLSI implementation of the router that delivers up to 1.17G words/s across the sixteen-chip network with less than 1µs jitter.

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Section: Neuromorphic Networkmentioning

confidence: 99%

Section: A Chp Specificationmentioning

confidence: 99%

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A Multicast Tree Router for Multichip Neuromorphic Systems

Merolla

Arthur

Alvarez

et al. 2014

IEEE Trans. Circuits Syst. I

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“…The packet-based address-event protocol that we have proposed is an important innovation for neuromorphic systems. For one, packets are able to bundle system-level information along with spike events without increasing the width of the link (as opposed to previous neuromorphic implementations [11]). This opens the door for creating multi-dimensional grids simply by inserting additional head words each time the packet traverses to higher dimensions.…”

Section: A Packet Protocolmentioning

confidence: 99%

“…1). 2 The grid (or mesh) architecture, which was first used in the context of neuromorphic systems by [11], implements a broadcast by relaying events between nearest neighbor chips; it offers an expandable solution without sacrificing latency. In addition to pointwise all-to-all connectivity (oblivious delivery), our implementation supports targeted and excluded delivery, and can easily be extended to support arbitrary connectivity with the inclusion of a look-up table (described in Section VII).…”

mentioning

confidence: 99%

Expandable Networks for Neuromorphic Chips

Merolla

Arthur

Shi

et al. 2007

IEEE Trans. Circuits Syst. I

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Abstract-We have developed a grid network that broadcasts spikes (binary events) in a multi-chip neuromorphic system by relaying them from chip to chip. The grid is expandable because, unlike a bus, its capacity does not decrease as more chips are added. The multiple relays do not increase latency because the grid's cycle-time is shorter than the bus. We describe an asynchronous relay implementation that automatically assigns chip-addresses to indicate the source of spikes, encoded as wordserial address-events. This design, which is integrated on each chip, connects neurons at corresponding locations on each of the chips (pointwise connectivity) and supports oblivious, targeted, and excluded delivery of spikes. Results from two chips fabricated in 0.25-µm technology are presented, showing word-rates up to 45.4 M events/s. I. ADDRESS-EVENT COMMUNICATIONNeuromorphic engineers attempt to capture the computational power and efficiency of biological neural systems in their hybrid analog-digital VLSI systems. These neuromorphic systems employ a similar design strategy as biology: local computations are performed in analog, and the results are communicated using all-or-none binary events (spikes). A typical neuromorphic chip consists of a 2-D array of bio-inspired circuits (core), which may include models of synapses [1], spatiotemporal filtering [2], and spike generation [3]; the array is surrounded by a transceiver that handles spike communication to and from the core through an off-chip link. Techniques to morph neural wetware into VLSI hardware have been described previously for analog circuits [4], [5] and spikebased communication [6].Neuromorphic chips routinely require tens of thousands of axonal connections to propagate spikes to and from the corefar too many to be implemented using dedicated wires. The address-event link, originally introduced by Mahowald and Sivilotti, implements these axonal connections using a timedivision-multiple-access (TDMA) link [7], [8]. Transceivers multiplex-demultiplex spikes over a few high-speed wires for efferent-afferent (outgoing-incoming) axons, respectively. For each event, the axon's identity is encoded with a unique binary word, an address event.

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