An asynchronous scan path concept for micropipelines using the bundled data convention

Schöber, Volker; Kiel, Thomas

doi:10.1109/test.1996.556965

Cited by 8 publications

(3 citation statements)

References 11 publications

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“…Moreover, different testing control schemes are presentedcalled scan test control logic (STCL) -for two and fourphase protocols. Schöber et Kiel also explores a scan path design for micropipeline circuits [10]. They also propose a fully asynchronous scan approach, which in no clock is used during normal and test mode.…”

Section: Related Workmentioning

confidence: 99%

At-speed DfT Architecture for Bundled-data Design

Guazzelli

Fesquet

2020

2020 IEEE International Test Conference (ITC)

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At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its timing constraints between control and data paths, Design for Testability (DfT) methodologies must test both control and data paths at the same time in order to guarantee the circuit correctness. As Process Voltage Temperature (PVT) variations significantly impact circuit design in newer CMOS technologies and low-power techniques such as voltage scaling, the timing constraints between control and data paths must be tested after fabrication not only under nominal conditions but through a range of operating conditions. However, this requirement demands modifications in the control and data paths, which are not straightforward and not desirable from a commercial standpoint due to its incompatibility with conventional testing tools. Even with the available testing methodologies for asynchronous circuits in the literature -by adapting the existing techniques for synchronous or creating new ones from scratch -those methodologies usually target the control or data path. This work explores an at-speed testing approach for bundled data circuits, targeting the micropipeline template. The main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in controllers, enabling circuit verification through available scan chains.

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Section: Related Workmentioning

confidence: 99%

At-speed DfT Architecture for Bundled-data Design

Guazzelli

Fesquet

2020

2020 IEEE International Test Conference (ITC)

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“…We do the latter, because it also enables us to test the data paths. Our scan DfT is synchronous [10] because of the lower costs, but self timed is also possible [11].…”

Section: Tailored High-quality Low-cost Dft Solutionmentioning

confidence: 99%

“…Testability for asynchronous circuits is getting mature. Synchronous partial scan solutions are built into asynchronous synthesis methodologies [7]- [10], and also self-timed solutions are available [11]. In addition to these externally controlled test structures, Built-In Self Test (BIST) has been applied to asynchronous micropipeline designs [12].…”

Section: Introductionmentioning

confidence: 99%

Defect-oriented testability for asynchronous ICs

Roncken

1999

Proc. IEEE

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For a CMOS manufacturing process, asynchronous IC's are similar to synchronous IC's. The defect density distributions are similar, and hence, so are the fault models and fault-detection methods. So, what makes us think that asynchronous circuits are much harder to test than synchronous circuits? Because the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? That may very well be a temporal hurdle. Many test methods have already been reevaluated and successfully adapted from the synchronous to the asynchronous test domain. The paper addresses one of the final hurdles: I DDQ testing. This type of test method, based on measuring the quiescent power supply current, is very effective for detecting (resistive) bridging faults in CMOS circuits. Detection of bridging faults is crucial, because they model the majority of today's manufacturing defects. I DDQ fault effects are sensitized in a particular state or set of states and can only be detected if we stop the circuit operation right there. This is a problem for asynchronous circuits, because their operation is self timed. In the paper, we quantify the impact of self timing on the effectiveness of I DDQ -based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do the same for logic voltage testing and stuck-at faults. The approach is illustrated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general.

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A BIST scheme for asynchronous logic

Alves¹,

França²,

Granja³

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

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An asynchronous scan path concept for micropipelines using the bundled data convention

Cited by 8 publications

References 11 publications

At-speed DfT Architecture for Bundled-data Design

At-speed DfT Architecture for Bundled-data Design

Defect-oriented testability for asynchronous ICs

A BIST scheme for asynchronous logic

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