Abstract. In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor.Next, we present the detailed design implementation and the various aspects of physical layout of different subblocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 m, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.

Objective:to analyze the correspondence between the actions contained in the fall prevention protocol of the Ministry of Health and the Nursing Interventions Classification (NIC) by a cross-mapping. Method:this is a descriptive study carried out in four stages: protocol survey, identification of NIC interventions related to nursing diagnosis, the risk of falls, cross-mapping, and validation of the mapping from the Delphi technique. Results:there were 51 actions identified in the protocol and 42 interventions in the NIC. Two rounds of mapping evaluation were carried out by the experts. There were 47 protocol actions corresponding to 25 NIC interventions. The NIC interventions that presented the highest correspondence with protocol actions were: fall prevention, environmental-safety control, and risk identification. Regarding the classification of similarity and comprehensiveness of the 47 actions of the protocol mapped, 44.7% were considered more detailed and specific than the NIC, 29.8% less specific than the NIC and 25.5% were classified as similar in significance to the NIC. Conclusion:most of the actions contained in the protocol are more specific and detailed, however, the NIC contemplates a greater diversity of interventions and may base a review of the protocol to increase actions related to falls prevention..

The growing volume of data produced continuously in the Cloud and at the Edge poses significant challenges for large-scale AI applications to extract and learn useful information from the data in a timely and efficient way. The goal of this article is to explore the use of computational storage to address such challenges by distributed near-data processing. We describe Newport, a high-performance and energy-efficient computational storage developed for realizing the full potential of in-storage processing. To the best of our knowledge, Newport is the first commodity SSD that can be configured to run a server-like operating system, greatly minimizing the effort for creating and maintaining applications running inside the storage. We analyze the benefits of using Newport by running complex AI applications such as image similarity search and object tracking on a large visual dataset. The results demonstrate that data-intensive AI workloads can be efficiently parallelized and offloaded, even to a small set of Newport drives with significant performance gains and energy savings. In addition, we introduce a comprehensive taxonomy of existing computational storage solutions together with a realistic cost analysis for high-volume production, giving a good big picture of the economic feasibility of the computational storage technology.

In this paper, the effects of simultaneous write access on the fault modeling of multiport RAMs are investigated. New fault models representing more accurately the actual faults in such memories are then defined. Subsequently, a general algorithm that ensures the detection of all faults belonging to the new fault model is proposed. Unfortunately, the obtained algorithms are of O(n/sup 2/) complexity which is not practical for real purposes. In order to reduce the complexity of the former test algorithm a topological approach has been developed. Finally, a BIST implementation of one of the proposed topological algorithms is presented

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