An early performance analysis of POWER7-IH HPC systems

Abstract

In this work we present a performance evaluation of the POWER7-IH processor and of integrated systems built from it. We describe the architecture of P7-IH with an emphasis on those characteristics that have a direct impact on the performance for large-scale HPC systems and applications. An important area of emphasis is the memory and communication subsystems and their impact on achievable application performance. The results from a set of micro-benchmarks are presented that include memory, communication and OS-noise characteristics. In addition the results from several production level applications are analyzed and their performance linked to the results of the micro-benchmarks through the use of accurate performance models. The models will also be employed in exploring the achievable performance of these applications on much larger systems.

Combining Static and Dynamic Data Coalescing in Unified Parallel C

“…The Hub Chip has seven different links for connecting nodes on the same drawer. These links have unidirectional bandwidth of 3 GB/s point-to-point between cores with a maximum of 24 GB/s aggregated unidirectional bandwidth [40]. In the streaming benchmark only one of the threads in the node communicates with a neighbouring node and therefore only one of the Hub links is used, decreasing the maximum bandwidth that is available.…”

The power 775 architecture at scale

“…We used a custom designed software stack that more tightly integrates communication with the application logic; such stacks need to be further explored. 8 When evaluating all-to-all communications, we noticed that naively communicating between all pairs of processes creates hotspots. Others have argued for support for randomized routing in hardware for reducing hotspots [18].…”

“…To the best of our knowledge, this approach to alleviating hotspots is novel. 8 We have also used such an integrated stack in the design of our Graph500 implementation [1], a non-trivial workload.…”

“…The POWER7 chip has been described in [15,16]; the network characteristics of the system are discussed in [6,25]. Finally, the performance of an early, drawer-level version of the P775 has been previously evaluated [8,22]. At 64 supernodes and 2 Pflop/s, this system is significantly larger than those in earlier studies [8,22].…”

A Theoretical Framework for Algorithm-Architecture Co-design

“…Our approach takes inspiration from prior work on highlevel performance analysis and modeling [3,[26][27][28]44], as well as the classical theory of circuit models and the area-time trade-offs studied in models based on very large-scale integration (VLSI) [37,49]. Our analysis is in many ways most similar to several recent theoretical exascale modeling studies [22,47], combined with trends analysis [34].…”