An Easily Implementable Approach to Increase the Energy Capability of DMOS Transistors

Abstract

DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.Index Terms-DMOS transistor, integrated power technologies, peak temperature, power dissipation density, power metaloxide-semiconductor field-effect transistor (MOSFET), thermal behavior, thermal runaway.

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

“…The new high-speed, high-integration, low-power switching circuit and power amplifier circuits required by various power conversion and energy processing devices are core devices based on SOI LDMOS devices [4]. However, on the one hand, the SOI power device isolates the surface of the device from the substrate due to the buried layer of the dielectric, thereby generating a self-heating effect, which affects the normal operation and reliability of the device [5][6]. On the other hand, at the Si / SiO2 interface of conventional SOI LDMOS structure, the critical breakdown electric field of Si is lower than that of SiO2, so the breakdown usually occurs at the Si layer of the interface, which makes the high critical breakdown electric field of SiO2 underutilized and the breakdown voltage of the device low [7][8].…”