2012 15th Euromicro Conference on Digital System Design 2012
DOI: 10.1109/dsd.2012.22
|View full text |Cite
|
Sign up to set email alerts
|

An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF

Abstract: Abstract-This paper presents an easy to design Physically Unclonable Function (PUF). The proposed PUF implementation is a loop composed of N identical and controllable delay chains which are serially assembled in a loop to create a single ring oscillator. The frequency discrepancies resulting from the oscillator driven by complementary combinations of the delay chains allows to characterize one device. The presented PUF, nicknamed the Loop PUF (LPUF), returns a frequency comparison of loops made of N delay cha… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
56
0

Year Published

2013
2013
2021
2021

Publication Types

Select...
5
3

Relationship

4
4

Authors

Journals

citations
Cited by 74 publications
(56 citation statements)
references
References 16 publications
0
56
0
Order By: Relevance
“…Bernard et al (2012) give no details of how they achieved the implementation of their RO PUF on Altera FPGAs. In Cherif, Danger, Guilley, and Bossuet (2012), another kind of delay-based PUF, called loop PUF, working with less gates than the RO PUF, is implemented for Altera FPGAs. They hint that "LogicLocks" and node location declarations were used, but no further details are given.…”
Section: Altera Cyclone Fpgamentioning
confidence: 99%
“…Bernard et al (2012) give no details of how they achieved the implementation of their RO PUF on Altera FPGAs. In Cherif, Danger, Guilley, and Bossuet (2012), another kind of delay-based PUF, called loop PUF, working with less gates than the RO PUF, is implemented for Altera FPGAs. They hint that "LogicLocks" and node location declarations were used, but no further details are given.…”
Section: Altera Cyclone Fpgamentioning
confidence: 99%
“…Most FPGA vendors suggest storing symmetric keys in a volatile memory area that requires external batteries [19] or one time programmable memory (anti-fuse) [19]. It is also possible to use a physical unclonable function (PUF like [28,29]) to generate and store keys, but these functions must be able to exchange their response (a PUF-ID) with the server before the configuration is encrypted [30]. Some academic works proposed a design for a trusted platform module (TPM) dedicated to FPGAs and reconfigurable architectures that can manage keys, and encrypt and decrypt the configuration, but that can also be used for cryptographic needs depending on the application [31,32].…”
Section: State Of the Art Of Secure Fpga Configurationmentioning
confidence: 99%
“…, ⌊n 2 D(n 1 , 3, 2)⌋} for all n 1 , n 2 > 0 except for (n 1 , n 2 ) ∈ {(6, 5), (7,3), (7,4), (7,5)}, whose values are listed below.…”
Section: Case 1: K = (4)mentioning
confidence: 99%
“…Multiply constant-weight codes have attracted recent attention due to an application in the design of certain physically unclonable functions (PUFs) [1], [2], [5]. Introduced by Pappu et al [6], PUFs provide innovative low-cost authentication methods that are derived from complex physical characteristics of electronic devices and have recently become an attractive option to provide security in low cost devices such as RFIDs and smart cards [5]- [8].…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation