Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs

Feiten, Linus; Spilla, A.; Sauer, Matthias; Schubert, Tobias; Becker, Bernd

doi:10.1080/19393555.2014.891281

Cited by 9 publications

(19 citation statements)

References 14 publications

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“…Although the reliability improves significantly with the temporal majority voting, it requires repeating PUF measurements which is, compared to our solutions, takes much longer due to the measurement time of the oscillators. Recent work also complies with our results and shows that on similar Altera FPGAs, the quality of RO based PUFs can change drastically and can have an anomalous characteristics [23]. However, the typical quality metrics for RO-PUFs on Xilinx FPGAs are much better than what is achieved on Altera FPGAs [13].…”

Section: Advanced Metrics Of Quality For Authentication Identifierssupporting

confidence: 89%

Hardware/software co-design of physical unclonable function based authentications on FPGAs

Aysu

Schaumont

2015

Microprocessors and Microsystems

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Physical Unclonable Functions (PUFs) enable the generation of device-unique, on-chip, and digital identifiers by exploiting the manufacturing process variation. The past decade has seen an extensive effort in PUF design. Yet, most PUF constructions are regarded as stand-alone hardware building blocks. In contrast, we propose PUF constructions that are tightly integrated into the design of a micro-processor. The proposed PUFs are essentially a collection of time-to-digital converters that are integrated into the custom instruction or memory-mapped interface of a processor. Therefore, the processor can issue the PUF challenges and collect the associated responses using instruction executions. This integration enables practical, run-time physical authentication and it allows flexible post-processing mechanisms using software. In this article, we describe the design, implementation, and the performance analysis details of such hardware/software co-designed authentication mechanisms on FPGAs. We propose two variants of the PUF architecture: a synchronous module that requires minimal place and route constraints utilizing the common clock of the SoC, and an asynchronous alternative that is independent of the clock but realized with a controlled placement. We implemented the synchronous architecture on the Altera Cyclone-IV FPGAs and performed a large-scale characterization on 55 boards. The asynchronous design is realized on the Xilinx Virtex-5 FPGAs and tested on 100 boards. Measurements reveal that the proposed solutions can authenticate trillions of devices and provide better performance than the ring oscillator based alternative.[1], tamper-resistant key storage [2], bitstream protection [3], and IP binding [4].

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Section: Advanced Metrics Of Quality For Authentication Identifierssupporting

confidence: 89%

Hardware/software co-design of physical unclonable function based authentications on FPGAs

Aysu

Schaumont

2015

Microprocessors and Microsystems

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“…The structure is equipped with a CRP generation process, where demultiplexers and multiplexers are placed before and after ROs, respectively. Therefore, the unequal route distances from ROs to counters caused inaccuracy in counting RO pulses, which were identified as locking phenomena [26,27] or jitter noise [28]. Meanwhile, this work proposes a modified RO-PUF structure that connects ROs directly to counters (no intermediary circuit between the ROs and the counters), as shown in Figure 1.…”

Section: Proposed Ro-pufmentioning

confidence: 99%

“…According to previous works, three-stage RO is less stable [28,[32][33][34]. The frequencies of ROs are varied, from 120 MHz to 200 MHz, leading to a standard deviation of 11.3 MHz, which is relatively high compared to the ROs, which are realized using higher stages, around 1 MHz [32,34].…”

Section: Ro Implementationsmentioning

confidence: 99%

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Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

et al. 2021

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The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF.

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“…Many studies have shown that the RO-PUF is the best candidate for FPGAs (eg. [18], [19], [20], [21]). Unfortunately, the RO-PUF has a security problem: it can be cloned using electromagnetic analysis [22] or RO cells can be locked using electromagnetic injections [23].…”

Section: Introductionmentioning

confidence: 99%

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF

Marchand

Bossuet

Mureddu

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

101

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Today, life is becoming increasingly connected. From TVs to smartphones, including vehicles, buildings, and household appliances, everything is interconnected in what we call the "Internet of Things" (IoT). IoT is now part of our life and we have to deal with it. More than 10 billion devices are already connected and five times more are expected to be deployed in the next five years. While deployment and integration of IoT is expanding, one of the main challenge is to provide practical solutions to security, privacy and trust issues in IoT. Protection and security mechanisms need to include features such as interoperability and scalability but also traceability, authentication and access control while remaining lightweight. Among the most promising approaches to such security mechanisms, physical unclonable functions (PUF) provide a unique identifier for similar but different integrated circuits using some of their physical characteristics. These types of functions can thus be used to authenticate integrated circuits, provide traceability and access control. This paper presents a comprehensive case study of the transient effect ring oscillator (TERO) PUF from its implementation on FPGAs to its complete characterization. The implementation of the PUF is detailed for two different families of FPGAs: Xilinx Spartan 6 and Altera Cyclone V. All the metrics used for the characterization are explained in detail and the results of the characterization include robustness to environmental parameters including variations in temperature and voltage. Finally, we compare our results with those obtained for another PUF: the ring oscillator (RO) PUF. All the design files are available online to ensure repeatability and enable comparison of our contribution with other studies.

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Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs

Cited by 9 publications

References 14 publications

Hardware/software co-design of physical unclonable function based authentications on FPGAs

Hardware/software co-design of physical unclonable function based authentications on FPGAs

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF

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