An educational environment for teaching a course in computer architecture and organization

Djordjevic, Jovan; Milenkovic, Aleksandar; Grbanovic, Nenad; Bojović, Miroslav

doi:10.1145/1275176.1275180

Cited by 6 publications

(9 citation statements)

References 3 publications

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“…The facilities offered by the Software Package of the Hierarchical Memory System are illustrated using the system with the interleaved memory. The hierarchical memory system environment is based on the originally developed and already used methodology for creating educational environments for teaching various topics in the field of computer architecture and organization [2]. The first step in the methodology is the logical design of the appropriate part of a computer system down to the register transfer level.…”

Section: Resultsmentioning

confidence: 99%

“…This problem the authors had treated in another paper concerning their course in Computer architecture and organization and came to the decision to devise and develop their own educational environment [2,3]. Based on the number of discussions conducted with the students that have used it in the laboratory experiments and the results of the exams, the authors are convinced that the educational environment has been a power aid in teaching the course in Computer architecture and organization.…”

Section: Introductionmentioning

confidence: 99%

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A hierarchical memory system environment

Djordjevic

Milenkovic

Prodanovic

1998

Proceedings of the 1998 Workshop on Computer Architecture Education - WCAE '98

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The paper presents an environment for teaching elements of a computer system memory hierarchy. It is made up of a hierarchical memory system, a reference manual, a software package and a set of laboratory experiments. The hierarchical memory system is devised to cover the virtual memory and translation lookaside buffer, the cache memory, and the main memory. The reference manual provides all implementation details with the appropriate circuits drawings and detailed descriptions. For the devised hierarchical memory system a software package, which includes the graphical simulator with the accompanying tools, is developed. They allow one to carry out the simulation down to the register transfer level by executing a set of laboratory experiments

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A hierarchical memory system environment

Djordjevic

Milenkovic

Prodanovic

1998

Proceedings of the 1998 Workshop on Computer Architecture Education - WCAE '98

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“…At the Faculty of Electrical Engineering, University of Belgrade, significant effort has been invested in developing educational systems and simulators for various topics in the area of computer architecture and organization including the memory system [11]. The initial version of an originally developed memory system was designed and the standalone simulator was written in Visual Basic a few years ago [12].…”

Section: 2005mentioning

confidence: 99%

A Memory System for Education

Djordjevic

Nikolić

Mitrović

2005

The Computer Journal

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The memory system is one of the core topics in computer architecture and organization. An important problem in teaching this topic is how to help students connect their theoretical knowledge of memory system concepts with the practical problems facing the designer of various parts of a memory system. A common approach to tackling this problem is to organize practical exercises in the laboratory using a memory system simulator. The existing simulators mainly focus on subtle memory system issues, such as cache performance, latency, coherence and consistency models in multiprocessor systems and do not admit a view of design details and internal activities within various parts of a memory system. This paper presents an originally developed memory system for education and its web-based simulator. The memory system includes the virtual memory and translation lookaside buffer, the cache memory and the interleaved main memory. The simulator facilitates a web-based clock-by-clock interactive simulation of the memory system, its visual presentation at the register-transfer level and navigation through parts of the system. They can be used for exercises in the laboratory and self-learning from home.

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“…On one hand, several educators have designed simpler, hypothetical architectures that embody the main principles of modern processor architectures although not all of their complexity, like DLX, introduced by Patterson and Hennessy in [3], or Ant, introduced by Ellard in [4]. On the other hand, numerous researchers/instructors involved in computer architecture have tackled this problem developing a variety of education tools for computer systems simulation [5,6,7,8,9,10].…”

Section: Introductionmentioning

confidence: 99%

Presentation and simulation of computer architectures

Vojinovic

Milentijević

Genov³

et al. 2004

FACTA U EE

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Understanding modern computer architectures requires a good knowledge of the dynamic behavior of processors. A new alternative platform for creating and delivering presentations that successfully combines positive issues of both general and special-purpose presentation tools for computer architectures is proposed in this paper. Proposed platform introduces the concept of dynamic usage of data providers during the presentation and creating slide templates instead of slide creation. Originally developed presentation/simulation tool SimArch that implements almost all key features from the new platform is described. SimArch is designed for teaching/research purposes and devoted to description and visualization of computer architectures. Crucial novelties in SimArch related to involving of slide templates, behavior cases and selection of examples are demonstrated on examples based on MIPS architecture subsets.

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An educational environment for teaching a course in computer architecture and organization

Cited by 6 publications

References 3 publications

A hierarchical memory system environment

A hierarchical memory system environment

A Memory System for Education

Presentation and simulation of computer architectures

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