An effective congestion driven placement framework

Abstract

We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability

“…In this technique, one switches from recursive bisection to "local" floorplanning where the fixed outline is determined by the bin. This is done for two main reasons: (i) to preserve wirelength [9], congestion [8] and delay [21] estimates that may have been performed early during top-down placement, and (ii) avoid legalizing a placement with overlapping macros.…”

“…The only work in the literature that describes top-down congestion estimates and uses them in placement assumes a grid structure [8]. Therefore we develop the following technique: before each round of partitioning, we overlay the entire placement region on a grid.…”

Routability-driven placement and white space allocation

“…This category includes bounding-box (BBOX)-based modeling [12], probabilistic analysis-based modeling [17,14], Rent's rule-based modeling [24], and pin density-based modeling [5]. TP-based modeling methods usually construct Steiner tree for each net in the netlist.…”

“…Depending on the specific stage, the congestion estimation method as well as the bin granularity may differ. Allocating white space to congested region can be achieved by inflating cells [5,14]. In BonnPlace [5], congestions of initial partitions are first estimated by taking both inter-region nets and intra-region nets into account.…”

“…Allocating white space to congested region can be achieved by inflating cells [5,14]. In BonnPlace [5], congestions of initial partitions are first estimated by taking both inter-region nets and intra-region nets into account. Congestion due to inter-region nets is estimated by a probabilistic method using a routing grid structure, and congestion due to intra-region nets is estimated by pin density within this region.…”