An effective DFM strategy requires accurate process and IP pre-characterization

DREAMS (DFM Rule EvAluation using Manufactured Silicon) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of DFM (design for manufacturability) rules using the results of logic diagnosis performed on failed ICs. DREAMS is an improvement over prior art in that the distribution of rule violations over the diagnosis candidates and the entire design are taken into account along with the nature of the failure (e.g., bridge versus open) to appropriately weight the rules. Silicon and simulation results demonstrate the efficacy of the DREAMS methodology. Specifically, virtual data is used to demonstrate that the DFM rule most responsible for failure can be reliably identified even in light of the ambiguity inherent to a nonideal diagnostic resolution, and a corresponding rule-violation distribution that is counter-intuitive. We also show that the combination of physically-aware diagnosis and the nature of the violated DFM rule can be used together to improve rule evaluation even further. Application of DREAMS to the diagnostic results from an in-production chip provides valuable insight in how specific DFM rules improve yield (or not) for a given design manufactured in particular facility. Finally, we also demonstrate that a significant artifact of DREAMS is a dramatic improvement in diagnostic resolution. This means that in addition to identifying the most ineffective DFM rule(s), validation of that outcome via physical failure analysis of failed chips can be eased due to the corresponding improvement in diagnostic resolution.

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DREAMS: DFM Rule EvAluation using Manufactured Silicon

Blanton

Wang

Xue

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Technology Platform for IC Design in Nano-scale CMOS

Yang

2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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On graceful degradation of microprocessors in presence of faults via resource banking

Rodrigues

Kundu

2011

2011 IEEE 17th International on-Line Testing Symposium

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Reliability and manufacturability have emerged as -billion transistor chips. In this paper, we investigate how to degrade a chip multiprocessor (CMP) gracefully in presence of faults, by keeping its architected functionality intact at the expense of some loss of performance. The proposed solution involves banking resources and functional units that allow partial shutdown to isolate faulty regions. Within a processor chip, resources can be classified into three broad classes, namely the large memory structures such as caches, TLB, register file, the small memory structures namely the reorder buffer, issue queue, load-store buffer etc. and the datapath and control logic. The large arrays are usually well protected by ECC. Recent research has suggested that large datapath units such as FPU and integer division units are good candidates for execution outsourcing to other working cores in CMP. In this paper, we focus on relatively small but critically important integer ALU unit and small array structures. Outsourcing ALU operations incur large performance penalty and small arrays are critical for control operations. The proposed solution is based on banking of array structures and execution units as well as reducing instruction fetch, issue and retire widths that allow individual bank(s) to be disabled for operation. Reduction in resource size diminishes performance but retains functionality. In this paper we present performance degradation data for shutting down one or more banks for various small array structures and ALU units. Simulation confirms gradual degradation with diminishing resource sizes. On average over all considered structures, performance loss of just 6% was observed for single bank failures.

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An effective DFM strategy requires accurate process and IP pre-characterization

Cited by 13 publications

References 7 publications

DREAMS: DFM Rule EvAluation using Manufactured Silicon

DREAMS: DFM Rule EvAluation using Manufactured Silicon

Technology Platform for IC Design in Nano-scale CMOS

On graceful degradation of microprocessors in presence of faults via resource banking

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