An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems

Papadimitriou, Kyprianos; Anyfantis, Antonis; Dollas, Apostolos

doi:10.1109/tim.2009.2026607

Cited by 30 publications

(29 citation statements)

References 7 publications

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“…The experimental results presented in [30] conclude that the reconfiguration speed is three orders of magnitude worse than the peak reconfiguration speed of the platform if a flash memory is used to store the configurations. In [31] the authors analyze the impact of the reconfigurations in the performance of the High-Performance Reconfigurable Computer Cray XD1, which includes one or several FPGAs and a conventional multiprocessor system.…”

Section: State-of-the-artmentioning

confidence: 94%

“…This is a valid assumption as long as the reconfiguration circuitry can write the data at the same speed that it receives it. In the examples analyzed in the literature ( [30] and [31]) the bottleneck was always the configuration memory, and the reconfiguration circuitry was never working at full capacity. Hence we can safely assume that the configurations are written "on the fly" and the process finishes just a few clock cycles after reading the last word.…”

Section: B Static Vs Dynamic Mapping Algorithms In Static Environmentsmentioning

confidence: 99%

See 1 more Smart Citation

Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

Clemente

Ramo

Resano

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can introduce important overheads, both in terms of energy consumption and time, especially when configurations are fetched from an external memory. In order to address this problem, this article presents a configuration memory hierarchy including two on-chip memory modules with different access time and energy consumption features. In addition, we have developed two configuration mapping algorithms that take advantage of these memories to reduce the system energy consumption, while increasing its performance. The first algorithm has been optimized for systems with reduced dynamic behavior, hence it optimizes the system for each given set of tasks. The second algorithm targets dynamic systems where the active tasks change unpredictably. Thus, its objective is also to decrease the pressure on the on-chip memories to reduce capacity conflicts.The presented results will demonstrate that, with the proper management, our configuration memory hierarchy leads to an energy consumption reduction up to 81% with respect to fetching the configurations from the external memory, while keeping the system performance very close to the ideal upperbound one.

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Section: State-of-the-artmentioning

confidence: 94%

Section: B Static Vs Dynamic Mapping Algorithms In Static Environmentsmentioning

confidence: 99%

Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

Clemente

Ramo

Resano

et al. 2014

IEEE Trans. VLSI Syst.

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“…RELATED WORK Four interesting recent articles [12], [13], [14], [15] have analyzed the impact of loading the configurations at run-time from a non-volatile external memory. The experimental results presented in [12] conclude that the reconfiguration speed is three orders of magnitude worse than the peak reconfiguration speed of the device if a flash memory is used to store the configurations. In [13] the authors analyze the impact of the reconfigurations in the performance of the High-Performance Reconfigurable Computer Cray XD1, including one or several FPGAs and a conventional multiprocessor system.…”

Section: Introductionmentioning

confidence: 99%

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

Clemente

Tejero

Chocano

et al. 2016

IEEE Trans. VLSI Syst.

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Abstract-The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip configuration memory is included in the system because it can reduce both the reconfiguration latency and its energy consumption. However, FPGA on-chip memory resources are very limited. Thus, it is very important to manage them effectively in order to improve the reconfiguration process as much as possible even when the size of the on-chip configuration memory is small. This paper presents a hardware implementation of an on-chip configuration memory controller that efficiently manages run-time reconfigurations. In order to optimize the use of the on-chip memory, this controller includes support to deal with configurations that have been divided into blocks of customizable size. When a reconfiguration must be carried out, our controller provides the blocks stored on-chip and looks for the remaining blocks by accessing to the off-chip configuration memory. Moreover, it dynamically decides which blocks must be stored on-chip. To this end, the designed controller implements a simple but efficient technique that allows maximizing the benefits of the on-chip memories. Experimental results will demonstrate that its implementation cost is very affordable and that it introduces negligible run-time management overheads.

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“…FPGA based system has the facility for remote updating of a device [2][3]. FPGA system has unique feature like dynamic swapping between hardware and software to improve the system performance [9][10]. However, the design of FPGA is much more complex due to the integration of hardware and software tool.…”

Section: Introductionmentioning

confidence: 99%

Microcontroller based remote updating system using voice channel of cellular network

Dalai

Chatterjee

Dey

et al. 2015

2015 IEEE Power, Communication and Information Technology Conference (PCITC)

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This paper presents a scheme of remote updating based on any existing cellular network. The scheme is successfully implemented on 8 bit general purpose microcontroller for quick prototyping and incorporating the remote update feature even for small applications in a cost effective manner. Existing cellular network is used to avoid the cost and hassles of creating and maintaining a dedicated network infrastructure. The updating system consists of two units. One is the central controlling unit located at a central place and the other is a remote standalone unit that is to be updated through this controlling unit as and when required. Both the units are provided with commercially available lowcost cellphones for establishing the communication during the update process. The remote unit consists of an additional updating microcontroller along with the main microcontroller. This updating microcontroller receives the code from the central unit through the cellphone attached to it and updates the main microcontroller of the remote unit. Two case studies for application of the remote updating scheme are presented in this paper. In one example, the program memory, i.e. the firmware, is updated, while in the other application, the nonvolatile EEPROM memory is updated in the main microcontroller of the remote unit through this remote updating scheme.

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An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems

Cited by 30 publications

References 7 publications

Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

Microcontroller based remote updating system using voice channel of cellular network

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